364 lines
14 KiB
ArmAsm
364 lines
14 KiB
ArmAsm
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/*
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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* Copyright (c) 2014 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/aarch64/asm.S"
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function ff_conv_flt_to_s16_neon, export=1
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subs x2, x2, #8
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ld1 {v0.4s}, [x1], #16
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fcvtzs v4.4s, v0.4s, #31
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ld1 {v1.4s}, [x1], #16
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fcvtzs v5.4s, v1.4s, #31
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b.eq 3f
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ands x12, x2, #~15
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b.eq 2f
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1: subs x12, x12, #16
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sqrshrn v4.4h, v4.4s, #16
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ld1 {v2.4s}, [x1], #16
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fcvtzs v6.4s, v2.4s, #31
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sqrshrn2 v4.8h, v5.4s, #16
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ld1 {v3.4s}, [x1], #16
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fcvtzs v7.4s, v3.4s, #31
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sqrshrn v6.4h, v6.4s, #16
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st1 {v4.8h}, [x0], #16
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sqrshrn2 v6.8h, v7.4s, #16
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ld1 {v0.4s}, [x1], #16
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fcvtzs v4.4s, v0.4s, #31
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ld1 {v1.4s}, [x1], #16
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fcvtzs v5.4s, v1.4s, #31
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st1 {v6.8h}, [x0], #16
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b.ne 1b
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ands x2, x2, #15
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b.eq 3f
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2: ld1 {v2.4s}, [x1], #16
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sqrshrn v4.4h, v4.4s, #16
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fcvtzs v6.4s, v2.4s, #31
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ld1 {v3.4s}, [x1], #16
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sqrshrn2 v4.8h, v5.4s, #16
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fcvtzs v7.4s, v3.4s, #31
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sqrshrn v6.4h, v6.4s, #16
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st1 {v4.8h}, [x0], #16
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sqrshrn2 v6.8h, v7.4s, #16
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st1 {v6.8h}, [x0]
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ret
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3: sqrshrn v4.4h, v4.4s, #16
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sqrshrn2 v4.8h, v5.4s, #16
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st1 {v4.8h}, [x0]
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ret
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endfunc
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function ff_conv_fltp_to_s16_2ch_neon, export=1
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ldp x4, x5, [x1]
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subs x2, x2, #8
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ld1 {v0.4s}, [x4], #16
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fcvtzs v4.4s, v0.4s, #31
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ld1 {v1.4s}, [x4], #16
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fcvtzs v5.4s, v1.4s, #31
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ld1 {v2.4s}, [x5], #16
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fcvtzs v6.4s, v2.4s, #31
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ld1 {v3.4s}, [x5], #16
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fcvtzs v7.4s, v3.4s, #31
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b.eq 3f
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ands x12, x2, #~15
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b.eq 2f
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1: subs x12, x12, #16
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ld1 {v16.4s}, [x4], #16
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fcvtzs v20.4s, v16.4s, #31
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sri v6.4s, v4.4s, #16
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ld1 {v17.4s}, [x4], #16
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fcvtzs v21.4s, v17.4s, #31
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ld1 {v18.4s}, [x5], #16
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fcvtzs v22.4s, v18.4s, #31
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ld1 {v19.4s}, [x5], #16
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sri v7.4s, v5.4s, #16
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st1 {v6.4s}, [x0], #16
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fcvtzs v23.4s, v19.4s, #31
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st1 {v7.4s}, [x0], #16
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sri v22.4s, v20.4s, #16
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ld1 {v0.4s}, [x4], #16
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sri v23.4s, v21.4s, #16
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st1 {v22.4s}, [x0], #16
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fcvtzs v4.4s, v0.4s, #31
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ld1 {v1.4s}, [x4], #16
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fcvtzs v5.4s, v1.4s, #31
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ld1 {v2.4s}, [x5], #16
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fcvtzs v6.4s, v2.4s, #31
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ld1 {v3.4s}, [x5], #16
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fcvtzs v7.4s, v3.4s, #31
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st1 {v23.4s}, [x0], #16
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b.ne 1b
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ands x2, x2, #15
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b.eq 3f
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2: sri v6.4s, v4.4s, #16
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ld1 {v0.4s}, [x4], #16
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fcvtzs v0.4s, v0.4s, #31
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ld1 {v1.4s}, [x4], #16
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fcvtzs v1.4s, v1.4s, #31
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ld1 {v2.4s}, [x5], #16
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fcvtzs v2.4s, v2.4s, #31
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sri v7.4s, v5.4s, #16
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ld1 {v3.4s}, [x5], #16
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fcvtzs v3.4s, v3.4s, #31
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sri v2.4s, v0.4s, #16
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st1 {v6.4s,v7.4s}, [x0], #32
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sri v3.4s, v1.4s, #16
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st1 {v2.4s,v3.4s}, [x0], #32
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ret
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3: sri v6.4s, v4.4s, #16
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sri v7.4s, v5.4s, #16
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st1 {v6.4s,v7.4s}, [x0]
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ret
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endfunc
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function ff_conv_fltp_to_s16_neon, export=1
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cmp w3, #2
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b.eq X(ff_conv_fltp_to_s16_2ch_neon)
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b.gt 1f
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ldr x1, [x1]
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b X(ff_conv_flt_to_s16_neon)
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1:
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cmp w3, #4
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lsl x12, x3, #1
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b.lt 4f
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5: // 4 channels
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ldp x4, x5, [x1], #16
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ldp x6, x7, [x1], #16
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mov w9, w2
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mov x8, x0
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ld1 {v4.4s}, [x4], #16
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fcvtzs v4.4s, v4.4s, #31
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ld1 {v5.4s}, [x5], #16
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fcvtzs v5.4s, v5.4s, #31
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ld1 {v6.4s}, [x6], #16
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fcvtzs v6.4s, v6.4s, #31
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ld1 {v7.4s}, [x7], #16
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fcvtzs v7.4s, v7.4s, #31
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6:
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subs w9, w9, #8
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ld1 {v0.4s}, [x4], #16
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fcvtzs v0.4s, v0.4s, #31
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sri v5.4s, v4.4s, #16
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ld1 {v1.4s}, [x5], #16
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fcvtzs v1.4s, v1.4s, #31
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sri v7.4s, v6.4s, #16
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ld1 {v2.4s}, [x6], #16
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fcvtzs v2.4s, v2.4s, #31
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zip1 v16.4s, v5.4s, v7.4s
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ld1 {v3.4s}, [x7], #16
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fcvtzs v3.4s, v3.4s, #31
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zip2 v17.4s, v5.4s, v7.4s
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st1 {v16.d}[0], [x8], x12
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sri v1.4s, v0.4s, #16
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st1 {v16.d}[1], [x8], x12
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sri v3.4s, v2.4s, #16
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st1 {v17.d}[0], [x8], x12
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zip1 v18.4s, v1.4s, v3.4s
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st1 {v17.d}[1], [x8], x12
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zip2 v19.4s, v1.4s, v3.4s
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b.eq 7f
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ld1 {v4.4s}, [x4], #16
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fcvtzs v4.4s, v4.4s, #31
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st1 {v18.d}[0], [x8], x12
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ld1 {v5.4s}, [x5], #16
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fcvtzs v5.4s, v5.4s, #31
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st1 {v18.d}[1], [x8], x12
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ld1 {v6.4s}, [x6], #16
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fcvtzs v6.4s, v6.4s, #31
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st1 {v19.d}[0], [x8], x12
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ld1 {v7.4s}, [x7], #16
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fcvtzs v7.4s, v7.4s, #31
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st1 {v19.d}[1], [x8], x12
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b 6b
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7:
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st1 {v18.d}[0], [x8], x12
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st1 {v18.d}[1], [x8], x12
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st1 {v19.d}[0], [x8], x12
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st1 {v19.d}[1], [x8], x12
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subs w3, w3, #4
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b.eq end
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cmp w3, #4
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add x0, x0, #8
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b.ge 5b
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4: // 2 channels
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cmp w3, #2
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b.lt 4f
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ldp x4, x5, [x1], #16
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mov w9, w2
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mov x8, x0
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tst w9, #8
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ld1 {v4.4s}, [x4], #16
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fcvtzs v4.4s, v4.4s, #31
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ld1 {v5.4s}, [x5], #16
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fcvtzs v5.4s, v5.4s, #31
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ld1 {v6.4s}, [x4], #16
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fcvtzs v6.4s, v6.4s, #31
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ld1 {v7.4s}, [x5], #16
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fcvtzs v7.4s, v7.4s, #31
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b.eq 6f
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subs w9, w9, #8
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b.eq 7f
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sri v5.4s, v4.4s, #16
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ld1 {v4.4s}, [x4], #16
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fcvtzs v4.4s, v4.4s, #31
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st1 {v5.s}[0], [x8], x12
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sri v7.4s, v6.4s, #16
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st1 {v5.s}[1], [x8], x12
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ld1 {v6.4s}, [x4], #16
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fcvtzs v6.4s, v6.4s, #31
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st1 {v5.s}[2], [x8], x12
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st1 {v5.s}[3], [x8], x12
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st1 {v7.s}[0], [x8], x12
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st1 {v7.s}[1], [x8], x12
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ld1 {v5.4s}, [x5], #16
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fcvtzs v5.4s, v5.4s, #31
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st1 {v7.s}[2], [x8], x12
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st1 {v7.s}[3], [x8], x12
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ld1 {v7.4s}, [x5], #16
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fcvtzs v7.4s, v7.4s, #31
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6:
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subs w9, w9, #16
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ld1 {v0.4s}, [x4], #16
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sri v5.4s, v4.4s, #16
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fcvtzs v0.4s, v0.4s, #31
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ld1 {v1.4s}, [x5], #16
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sri v7.4s, v6.4s, #16
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st1 {v5.s}[0], [x8], x12
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st1 {v5.s}[1], [x8], x12
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fcvtzs v1.4s, v1.4s, #31
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st1 {v5.s}[2], [x8], x12
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st1 {v5.s}[3], [x8], x12
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ld1 {v2.4s}, [x4], #16
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st1 {v7.s}[0], [x8], x12
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fcvtzs v2.4s, v2.4s, #31
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st1 {v7.s}[1], [x8], x12
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ld1 {v3.4s}, [x5], #16
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st1 {v7.s}[2], [x8], x12
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fcvtzs v3.4s, v3.4s, #31
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st1 {v7.s}[3], [x8], x12
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sri v1.4s, v0.4s, #16
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sri v3.4s, v2.4s, #16
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b.eq 6f
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ld1 {v4.4s}, [x4], #16
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st1 {v1.s}[0], [x8], x12
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fcvtzs v4.4s, v4.4s, #31
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st1 {v1.s}[1], [x8], x12
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ld1 {v5.4s}, [x5], #16
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st1 {v1.s}[2], [x8], x12
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fcvtzs v5.4s, v5.4s, #31
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st1 {v1.s}[3], [x8], x12
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ld1 {v6.4s}, [x4], #16
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st1 {v3.s}[0], [x8], x12
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fcvtzs v6.4s, v6.4s, #31
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st1 {v3.s}[1], [x8], x12
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ld1 {v7.4s}, [x5], #16
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st1 {v3.s}[2], [x8], x12
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fcvtzs v7.4s, v7.4s, #31
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st1 {v3.s}[3], [x8], x12
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b.gt 6b
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6:
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st1 {v1.s}[0], [x8], x12
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st1 {v1.s}[1], [x8], x12
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st1 {v1.s}[2], [x8], x12
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st1 {v1.s}[3], [x8], x12
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st1 {v3.s}[0], [x8], x12
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st1 {v3.s}[1], [x8], x12
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st1 {v3.s}[2], [x8], x12
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st1 {v3.s}[3], [x8], x12
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b 8f
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7:
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sri v5.4s, v4.4s, #16
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sri v7.4s, v6.4s, #16
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st1 {v5.s}[0], [x8], x12
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st1 {v5.s}[1], [x8], x12
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st1 {v5.s}[2], [x8], x12
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st1 {v5.s}[3], [x8], x12
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st1 {v7.s}[0], [x8], x12
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|
st1 {v7.s}[1], [x8], x12
|
||
|
|
st1 {v7.s}[2], [x8], x12
|
||
|
|
st1 {v7.s}[3], [x8], x12
|
||
|
|
8:
|
||
|
|
subs w3, w3, #2
|
||
|
|
add x0, x0, #4
|
||
|
|
b.eq end
|
||
|
|
|
||
|
|
4: // 1 channel
|
||
|
|
ldr x4, [x1]
|
||
|
|
tst w2, #8
|
||
|
|
mov w9, w2
|
||
|
|
mov x5, x0
|
||
|
|
ld1 {v0.4s}, [x4], #16
|
||
|
|
fcvtzs v0.4s, v0.4s, #31
|
||
|
|
ld1 {v1.4s}, [x4], #16
|
||
|
|
fcvtzs v1.4s, v1.4s, #31
|
||
|
|
b.ne 8f
|
||
|
|
6:
|
||
|
|
subs w9, w9, #16
|
||
|
|
ld1 {v2.4s}, [x4], #16
|
||
|
|
fcvtzs v2.4s, v2.4s, #31
|
||
|
|
ld1 {v3.4s}, [x4], #16
|
||
|
|
fcvtzs v3.4s, v3.4s, #31
|
||
|
|
st1 {v0.h}[1], [x5], x12
|
||
|
|
st1 {v0.h}[3], [x5], x12
|
||
|
|
st1 {v0.h}[5], [x5], x12
|
||
|
|
st1 {v0.h}[7], [x5], x12
|
||
|
|
st1 {v1.h}[1], [x5], x12
|
||
|
|
st1 {v1.h}[3], [x5], x12
|
||
|
|
st1 {v1.h}[5], [x5], x12
|
||
|
|
st1 {v1.h}[7], [x5], x12
|
||
|
|
b.eq 7f
|
||
|
|
ld1 {v0.4s}, [x4], #16
|
||
|
|
fcvtzs v0.4s, v0.4s, #31
|
||
|
|
ld1 {v1.4s}, [x4], #16
|
||
|
|
fcvtzs v1.4s, v1.4s, #31
|
||
|
|
7:
|
||
|
|
st1 {v2.h}[1], [x5], x12
|
||
|
|
st1 {v2.h}[3], [x5], x12
|
||
|
|
st1 {v2.h}[5], [x5], x12
|
||
|
|
st1 {v2.h}[7], [x5], x12
|
||
|
|
st1 {v3.h}[1], [x5], x12
|
||
|
|
st1 {v3.h}[3], [x5], x12
|
||
|
|
st1 {v3.h}[5], [x5], x12
|
||
|
|
st1 {v3.h}[7], [x5], x12
|
||
|
|
b.gt 6b
|
||
|
|
ret
|
||
|
|
8:
|
||
|
|
subs w9, w9, #8
|
||
|
|
st1 {v0.h}[1], [x5], x12
|
||
|
|
st1 {v0.h}[3], [x5], x12
|
||
|
|
st1 {v0.h}[5], [x5], x12
|
||
|
|
st1 {v0.h}[7], [x5], x12
|
||
|
|
st1 {v1.h}[1], [x5], x12
|
||
|
|
st1 {v1.h}[3], [x5], x12
|
||
|
|
st1 {v1.h}[5], [x5], x12
|
||
|
|
st1 {v1.h}[7], [x5], x12
|
||
|
|
b.eq end
|
||
|
|
ld1 {v0.4s}, [x4], #16
|
||
|
|
fcvtzs v0.4s, v0.4s, #31
|
||
|
|
ld1 {v1.4s}, [x4], #16
|
||
|
|
fcvtzs v1.4s, v1.4s, #31
|
||
|
|
b 6b
|
||
|
|
end:
|
||
|
|
ret
|
||
|
|
endfunc
|