182 lines
2.8 KiB
ArmAsm
182 lines
2.8 KiB
ArmAsm
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#include "x86_arch.h"
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.section .ctors
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.p2align 3
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.quad OPENSSL_cpuid_setup
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.text
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.globl OPENSSL_atomic_add
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.def OPENSSL_atomic_add; .scl 2; .type 32; .endef
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.p2align 4
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OPENSSL_atomic_add:
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movl (%rdi),%eax
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.Lspin: leaq (%rsi,%rax,1),%r8
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.byte 0xf0
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cmpxchgl %r8d,(%rdi)
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jne .Lspin
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movl %r8d,%eax
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.byte 0x48,0x98
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retq
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.globl OPENSSL_ia32_cpuid
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.def OPENSSL_ia32_cpuid; .scl 2; .type 32; .endef
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.p2align 4
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OPENSSL_ia32_cpuid:
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movq %rbx,%r8
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xorl %eax,%eax
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cpuid
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movl %eax,%r11d
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xorl %eax,%eax
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cmpl $1970169159,%ebx
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setne %al
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movl %eax,%r9d
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cmpl $1231384169,%edx
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setne %al
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orl %eax,%r9d
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cmpl $1818588270,%ecx
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setne %al
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orl %eax,%r9d
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jz .Lintel
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cmpl $1752462657,%ebx
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setne %al
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movl %eax,%r10d
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cmpl $1769238117,%edx
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setne %al
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orl %eax,%r10d
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cmpl $1145913699,%ecx
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setne %al
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orl %eax,%r10d
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jnz .Lintel
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movl $2147483648,%eax
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cpuid
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cmpl $2147483649,%eax
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jb .Lintel
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movl %eax,%r10d
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movl $2147483649,%eax
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cpuid
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andl $IA32CAP_MASK1_AMD_XOP,%r9d
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orl $1,%r9d
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cmpl $2147483656,%r10d
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jb .Lintel
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movl $2147483656,%eax
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cpuid
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movzbq %cl,%r10
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incq %r10
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movl $1,%eax
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cpuid
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btl $IA32CAP_BIT0_HT,%edx
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jnc .Lgeneric
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shrl $16,%ebx
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cmpb %r10b,%bl
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ja .Lgeneric
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xorl $IA32CAP_MASK0_HT,%edx
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jmp .Lgeneric
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.Lintel:
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cmpl $4,%r11d
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movl $-1,%r10d
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jb .Lnocacheinfo
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movl $4,%eax
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movl $0,%ecx
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cpuid
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movl %eax,%r10d
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shrl $14,%r10d
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andl $4095,%r10d
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.Lnocacheinfo:
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movl $1,%eax
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cpuid
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andl $(~(IA32CAP_MASK0_INTELP4 | IA32CAP_MASK0_INTEL)),%edx
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cmpl $0,%r9d
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jne .Lnotintel
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orl $IA32CAP_MASK0_INTEL,%edx
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andb $15,%ah
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cmpb $15,%ah
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jne .Lnotintel
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orl $IA32CAP_MASK0_INTELP4,%edx
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.Lnotintel:
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btl $IA32CAP_BIT0_HT,%edx
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jnc .Lgeneric
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xorl $IA32CAP_MASK0_HT,%edx
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cmpl $0,%r10d
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je .Lgeneric
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orl $IA32CAP_MASK0_HT,%edx
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shrl $16,%ebx
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cmpb $1,%bl
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ja .Lgeneric
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xorl $IA32CAP_MASK0_HT,%edx
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.Lgeneric:
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andl $IA32CAP_MASK1_AMD_XOP,%r9d
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andl $(~IA32CAP_MASK1_AMD_XOP),%ecx
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orl %ecx,%r9d
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movl %edx,%r10d
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btl $IA32CAP_BIT1_OSXSAVE,%r9d
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jnc .Lclear_avx
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xorl %ecx,%ecx
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.byte 0x0f,0x01,0xd0
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andl $6,%eax
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cmpl $6,%eax
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je .Ldone
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.Lclear_avx:
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movl $(~(IA32CAP_MASK1_AVX | IA32CAP_MASK1_FMA3 | IA32CAP_MASK1_AMD_XOP)),%eax
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andl %eax,%r9d
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.Ldone:
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shlq $32,%r9
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movl %r10d,%eax
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movq %r8,%rbx
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orq %r9,%rax
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retq
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.globl OPENSSL_wipe_cpu
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.def OPENSSL_wipe_cpu; .scl 2; .type 32; .endef
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.p2align 4
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OPENSSL_wipe_cpu:
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pxor %xmm0,%xmm0
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pxor %xmm1,%xmm1
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pxor %xmm2,%xmm2
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pxor %xmm3,%xmm3
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pxor %xmm4,%xmm4
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pxor %xmm5,%xmm5
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pxor %xmm6,%xmm6
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pxor %xmm7,%xmm7
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pxor %xmm8,%xmm8
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pxor %xmm9,%xmm9
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pxor %xmm10,%xmm10
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pxor %xmm11,%xmm11
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pxor %xmm12,%xmm12
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pxor %xmm13,%xmm13
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pxor %xmm14,%xmm14
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pxor %xmm15,%xmm15
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xorq %rcx,%rcx
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xorq %rdx,%rdx
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xorq %rsi,%rsi
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xorq %rdi,%rdi
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xorq %r8,%r8
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xorq %r9,%r9
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xorq %r10,%r10
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xorq %r11,%r11
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leaq 8(%rsp),%rax
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retq
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