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early-access version 1730

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pineappleEA
2021-05-30 08:36:49 +02:00
parent b09a4af601
commit 146ca66c3e
668 changed files with 155049 additions and 791 deletions
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141
externals/dynarmic/tests/A32/fuzz_arm.cpp vendored
View File

@@ -11,24 +11,24 @@
#include <vector>
#include <catch.hpp>
#include <dynarmic/A32/a32.h>
#include "common/common_types.h"
#include "common/fp/fpcr.h"
#include "common/fp/fpsr.h"
#include "common/llvm_disassemble.h"
#include "common/scope_exit.h"
#include "frontend/A32/ITState.h"
#include "frontend/A32/location_descriptor.h"
#include "frontend/A32/translate/translate.h"
#include "frontend/A32/types.h"
#include "frontend/ir/basic_block.h"
#include "frontend/ir/location_descriptor.h"
#include "frontend/ir/opcodes.h"
#include "fuzz_util.h"
#include "rand_int.h"
#include "testenv.h"
#include "unicorn_emu/a32_unicorn.h"
#include "../fuzz_util.h"
#include "../rand_int.h"
#include "../unicorn_emu/a32_unicorn.h"
#include "./testenv.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/llvm_disassemble.h"
#include "dynarmic/common/scope_exit.h"
#include "dynarmic/frontend/A32/ITState.h"
#include "dynarmic/frontend/A32/location_descriptor.h"
#include "dynarmic/frontend/A32/translate/translate.h"
#include "dynarmic/frontend/A32/types.h"
#include "dynarmic/interface/A32/a32.h"
#include "dynarmic/ir/basic_block.h"
#include "dynarmic/ir/location_descriptor.h"
#include "dynarmic/ir/opcodes.h"
// Must be declared last for all necessary operator<< to be declared prior to this.
#include <fmt/format.h>
@@ -79,12 +79,12 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
static const struct InstructionGeneratorInfo {
std::vector<InstructionGenerator> generators;
std::vector<InstructionGenerator> invalid;
} instructions = []{
const std::vector<std::tuple<std::string, const char*>> list {
} instructions = [] {
const std::vector<std::tuple<std::string, const char*>> list{
#define INST(fn, name, bitstring) {#fn, bitstring},
#include "frontend/A32/decoder/arm.inc"
#include "frontend/A32/decoder/asimd.inc"
#include "frontend/A32/decoder/vfp.inc"
#include "dynarmic/frontend/A32/decoder/arm.inc"
#include "dynarmic/frontend/A32/decoder/asimd.inc"
#include "dynarmic/frontend/A32/decoder/vfp.inc"
#undef INST
};
@@ -92,7 +92,7 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
std::vector<InstructionGenerator> invalid;
// List of instructions not to test
static constexpr std::array do_not_test {
static constexpr std::array do_not_test{
// Translating load/stores
"arm_LDRBT", "arm_LDRBT", "arm_LDRHT", "arm_LDRHT", "arm_LDRSBT", "arm_LDRSBT", "arm_LDRSHT", "arm_LDRSHT", "arm_LDRT", "arm_LDRT",
"arm_STRBT", "arm_STRBT", "arm_STRHT", "arm_STRHT", "arm_STRT", "arm_STRT",
@@ -117,9 +117,9 @@ u32 GenRandomArmInst(u32 pc, bool is_last_inst) {
// FPSCR is inaccurate
"vfp_VMRS",
// Incorrect Unicorn implementations
"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly.
"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly.
};
for (const auto& [fn, bitstring] : list) {
@@ -150,11 +150,23 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
static const struct InstructionGeneratorInfo {
std::vector<InstructionGenerator> generators;
std::vector<InstructionGenerator> invalid;
} instructions = []{
const std::vector<std::tuple<std::string, const char*>> list {
} instructions = [] {
const std::vector<std::tuple<std::string, const char*>> list{
#define INST(fn, name, bitstring) {#fn, bitstring},
#include "frontend/A32/decoder/thumb16.inc"
#include "frontend/A32/decoder/thumb32.inc"
#include "dynarmic/frontend/A32/decoder/thumb16.inc"
#include "dynarmic/frontend/A32/decoder/thumb32.inc"
#undef INST
};
const std::vector<std::tuple<std::string, const char*>> vfp_list{
#define INST(fn, name, bitstring) {#fn, bitstring},
#include "dynarmic/frontend/A32/decoder/vfp.inc"
#undef INST
};
const std::vector<std::tuple<std::string, const char*>> asimd_list{
#define INST(fn, name, bitstring) {#fn, bitstring},
#include "dynarmic/frontend/A32/decoder/asimd.inc"
#undef INST
};
@@ -162,16 +174,41 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
std::vector<InstructionGenerator> invalid;
// List of instructions not to test
static constexpr std::array do_not_test {
static constexpr std::array do_not_test{
"thumb16_BKPT",
"thumb16_IT",
"thumb16_SETEND",
// Exclusive load/stores
"thumb32_LDREX",
"thumb32_LDREXB",
"thumb32_LDREXD",
"thumb32_LDREXH",
"thumb32_STREX",
"thumb32_STREXB",
"thumb32_STREXD",
"thumb32_STREXH",
// FPSCR is inaccurate
"vfp_VMRS",
// Unicorn is incorrect?
"thumb32_MRS_reg",
// Unicorn has incorrect implementation (incorrect rounding and unsets CPSR.T??)
"vfp_VCVT_to_fixed",
"vfp_VCVT_from_fixed",
"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
// Coprocessor
"thumb32_CDP",
"thumb32_LDC",
"thumb32_MCR",
"thumb32_MCRR",
"thumb32_MRC",
"thumb32_MRRC",
"thumb32_STC",
};
for (const auto& [fn, bitstring] : list) {
@@ -181,6 +218,34 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
}
generators.emplace_back(InstructionGenerator{bitstring});
}
for (const auto& [fn, bs] : vfp_list) {
std::string bitstring = bs;
if (bitstring.substr(0, 4) == "cccc" || bitstring.substr(0, 4) == "----") {
bitstring.replace(0, 4, "1110");
}
if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
continue;
}
generators.emplace_back(InstructionGenerator{bitstring.c_str()});
}
for (const auto& [fn, bs] : asimd_list) {
std::string bitstring = bs;
if (bitstring.substr(0, 7) == "1111001") {
const char U = bitstring[7];
bitstring.replace(0, 8, "111-1111");
bitstring[3] = U;
} else if (bitstring.substr(0, 8) == "11110100") {
bitstring.replace(0, 8, "11111001");
} else {
ASSERT_FALSE("Unhandled ASIMD instruction: {} {}", fn, bs);
}
if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
invalid.emplace_back(InstructionGenerator{bitstring.c_str()});
continue;
}
generators.emplace_back(InstructionGenerator{bitstring.c_str()});
}
return InstructionGeneratorInfo{generators, invalid};
}();
@@ -191,13 +256,13 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
if (ShouldTestInst(is_four_bytes ? Common::SwapHalves32(inst) : inst, pc, true, is_last_inst, it_state)) {
if (is_four_bytes)
return { static_cast<u16>(inst >> 16), static_cast<u16>(inst) };
return { static_cast<u16>(inst) };
return {static_cast<u16>(inst >> 16), static_cast<u16>(inst)};
return {static_cast<u16>(inst)};
}
}
}
template <typename TestEnv>
template<typename TestEnv>
Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) {
Dynarmic::A32::UserConfig user_config;
user_config.optimizations &= ~OptimizationFlag::FastDispatch;
@@ -206,7 +271,7 @@ Dynarmic::A32::UserConfig GetUserConfig(TestEnv& testenv) {
return user_config;
}
template <typename TestEnv>
template<typename TestEnv>
static void RunTestInstance(Dynarmic::A32::Jit& jit,
A32Unicorn<TestEnv>& uni,
TestEnv& jit_env,
@@ -250,7 +315,7 @@ static void RunTestInstance(Dynarmic::A32::Jit& jit,
jit_env.ticks_left = ticks_left;
jit.Run();
uni_env.ticks_left = instructions.size(); // Unicorn counts thumb instructions weirdly.
uni_env.ticks_left = instructions.size(); // Unicorn counts thumb instructions weirdly.
uni.Run();
SCOPE_FAIL {
@@ -335,7 +400,7 @@ static void RunTestInstance(Dynarmic::A32::Jit& jit,
REQUIRE(uni_env.modified_memory == jit_env.modified_memory);
REQUIRE(uni_env.interrupts.empty());
}
} // Anonymous namespace
} // Anonymous namespace
TEST_CASE("A32: Single random arm instruction", "[arm]") {
ArmTestEnv jit_env{};
@@ -515,7 +580,7 @@ TEST_CASE("A32: Test thumb IT instruction", "[thumb]") {
}
// Emit IT instruction
A32::ITState it_state = [&]{
A32::ITState it_state = [&] {
while (true) {
const u16 imm8 = RandInt<u16>(0, 0xFF);
if (Common::Bits<0, 3>(imm8) == 0b0000 || Common::Bits<4, 7>(imm8) == 0b1111 || (Common::Bits<4, 7>(imm8) == 0b1110 && Common::BitCount(Common::Bits<0, 3>(imm8)) != 1)) {

255
externals/dynarmic/tests/A32/fuzz_thumb.cpp vendored
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@@ -14,20 +14,19 @@
#include <catch.hpp>
#include <dynarmic/A32/a32.h>
#include "common/bit_util.h"
#include "common/common_types.h"
#include "frontend/A32/disassembler/disassembler.h"
#include "frontend/A32/FPSCR.h"
#include "frontend/A32/location_descriptor.h"
#include "frontend/A32/PSR.h"
#include "frontend/A32/translate/translate.h"
#include "frontend/ir/basic_block.h"
#include "ir_opt/passes.h"
#include "rand_int.h"
#include "testenv.h"
#include "unicorn_emu/a32_unicorn.h"
#include "../rand_int.h"
#include "../unicorn_emu/a32_unicorn.h"
#include "./testenv.h"
#include "dynarmic/common/bit_util.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/frontend/A32/FPSCR.h"
#include "dynarmic/frontend/A32/PSR.h"
#include "dynarmic/frontend/A32/disassembler/disassembler.h"
#include "dynarmic/frontend/A32/location_descriptor.h"
#include "dynarmic/frontend/A32/translate/translate.h"
#include "dynarmic/interface/A32/a32.h"
#include "dynarmic/ir/basic_block.h"
#include "dynarmic/ir/opt/passes.h"
using namespace Dynarmic;
@@ -42,7 +41,9 @@ using WriteRecords = std::map<u32, u8>;
struct ThumbInstGen final {
public:
ThumbInstGen(std::string_view format, std::function<bool(u32)> is_valid = [](u32){ return true; }) : is_valid(is_valid) {
ThumbInstGen(
std::string_view format, std::function<bool(u32)> is_valid = [](u32) { return true; })
: is_valid(is_valid) {
REQUIRE((format.size() == 16 || format.size() == 32));
const auto bit_size = format.size();
@@ -96,18 +97,14 @@ private:
std::function<bool(u32)> is_valid;
};
static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit,
const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit, const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
const auto interp_regs = uni.GetRegisters();
const auto jit_regs = jit.Regs();
return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) &&
uni.GetCpsr() == jit.Cpsr() &&
interp_write_records == jit_write_records;
return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) && uni.GetCpsr() == jit.Cpsr() && interp_write_records == jit_write_records;
}
static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs,
size_t instruction_count, size_t instructions_to_execute_count) {
static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) {
uni.ClearPageCache();
jit.ClearCache();
@@ -178,7 +175,7 @@ static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<Th
size_t num_insts = 0;
while (num_insts < instructions_to_execute_count) {
A32::LocationDescriptor descriptor = {u32(num_insts * 4), cpsr, A32::FPSCR{}};
IR::Block ir_block = A32::Translate(descriptor, [&test_env](u32 vaddr) { return test_env.MemoryReadCode(vaddr); }, {});
IR::Block ir_block = A32::Translate(descriptor, &test_env, {});
Optimization::A32GetSetElimination(ir_block);
Optimization::DeadCodeElimination(ir_block);
Optimization::A32ConstantMemoryReads(ir_block, &test_env);
@@ -202,7 +199,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to
// Prepare memory.
test_env.code_mem.resize(instruction_count + 1);
test_env.code_mem.back() = 0xE7FE; // b +#0
test_env.code_mem.back() = 0xE7FE; // b +#0
// Prepare test subjects
A32Unicorn uni{test_env};
@@ -210,7 +207,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to
for (size_t run_number = 0; run_number < run_count; run_number++) {
ThumbTestEnv::RegisterArray initial_regs;
std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
initial_regs[15] = 0;
std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator);
@@ -225,7 +222,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
// Prepare memory.
// A Thumb-32 instruction is 32-bits so we multiply our count
test_env.code_mem.resize(instruction_count * 2 + 1);
test_env.code_mem.back() = 0xE7FE; // b +#0
test_env.code_mem.back() = 0xE7FE; // b +#0
// Prepare test subjects
A32Unicorn uni{test_env};
@@ -233,7 +230,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
for (size_t run_number = 0; run_number < run_count; run_number++) {
ThumbTestEnv::RegisterArray initial_regs;
std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
initial_regs[15] = 0;
for (size_t i = 0; i < instruction_count; i++) {
@@ -251,44 +248,44 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
const std::array instructions = {
ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
ThumbInstGen("010000ooooxxxxxx"), // Data Processing
ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
[](u32 inst){ return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
[](u32 inst){ return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
ThumbInstGen("1011101000xxxxxx"), // REV
ThumbInstGen("1011101001xxxxxx"), // REV16
ThumbInstGen("1011101011xxxxxx"), // REVSH
ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
ThumbInstGen("1011010xxxxxxxxx", // PUSH
[](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
[](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
ThumbInstGen("010000ooooxxxxxx"), // Data Processing
ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
[](u32 inst) { return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
[](u32 inst) { return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
ThumbInstGen("1011101000xxxxxx"), // REV
ThumbInstGen("1011101001xxxxxx"), // REV16
ThumbInstGen("1011101011xxxxxx"), // REVSH
ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
ThumbInstGen("1011010xxxxxxxxx", // PUSH
[](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
[](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
[](u32 inst) {
// Ensure that the architecturally undefined case of
// the base register being within the list isn't hit.
const u32 rn = Common::Bits<8, 10>(inst);
return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0;
}),
// TODO: We should properly test against swapped
// endianness cases, however Unicorn doesn't
// expose the intended endianness of a load/store
// operation to memory through its hooks.
// TODO: We should properly test against swapped
// endianness cases, however Unicorn doesn't
// expose the intended endianness of a load/store
// operation to memory through its hooks.
#if 0
ThumbInstGen("101101100101x000"), // SETEND
#endif
@@ -319,11 +316,11 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16]") {
const std::array instructions = {
// TODO: We currently can't test BX/BLX as we have
// no way of preventing the unpredictable
// condition from occurring with the current interface.
// (bits zero and one within the specified register
// must not be address<1:0> == '10'.
// TODO: We currently can't test BX/BLX as we have
// no way of preventing the unpredictable
// condition from occurring with the current interface.
// (bits zero and one within the specified register
// must not be address<1:0> == '10'.
#if 0
ThumbInstGen("01000111xmmmm000", // BLX/BX
[](u32 inst){
@@ -331,21 +328,21 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
return Rm != 15;
}),
#endif
ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
ThumbInstGen("11100xxxxxxxxxxx"), // B
ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
[](u32 inst){
ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
ThumbInstGen("11100xxxxxxxxxxx"), // B
ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
[](u32 inst) {
const u32 c = Common::Bits<9, 12>(inst);
return c < 0b1110; // Don't want SWI or undefined instructions.
return c < 0b1110; // Don't want SWI or undefined instructions.
}),
ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
ThumbInstGen("10110110011x0xxx"), // CPS
ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
ThumbInstGen("10110110011x0xxx"), // CPS
// TODO: We currently have no control over the generated
// values when creating new pages, so we can't
// reliably test this yet.
// TODO: We currently have no control over the generated
// values when creating new pages, so we can't
// reliably test this yet.
#if 0
ThumbInstGen("10111101xxxxxxxx"), // POP (R = 1)
#endif
@@ -369,122 +366,122 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
};
const std::array instructions = {
ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
[](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8
ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX
ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8
ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16
ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
[](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
[](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
[](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
[](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX
ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8
ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8
ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8
ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX
ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8
ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16
ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
three_reg_not_r15),
};
@@ -510,7 +507,7 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu
A32Unicorn<ThumbTestEnv> uni{test_env};
A32::Jit jit{GetUserConfig(&test_env)};
constexpr ThumbTestEnv::RegisterArray initial_regs {
constexpr ThumbTestEnv::RegisterArray initial_regs{
0xe90ecd70,
0x3e3b73c3,
0x571616f9,
@@ -530,12 +527,12 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu
};
test_env.code_mem = {
0x40B8, // lsls r0, r7, #0
0x01CA, // lsls r2, r1, #7
0x83A1, // strh r1, [r4, #28]
0x708A, // strb r2, [r1, #2]
0xBCC4, // pop {r2, r6, r7}
0xE7FE, // b +#0
0x40B8, // lsls r0, r7, #0
0x01CA, // lsls r2, r1, #7
0x83A1, // strh r1, [r4, #28]
0x708A, // strb r2, [r1, #2]
0xBCC4, // pop {r2, r6, r7}
0xE7FE, // b +#0
};
RunInstance(1, test_env, uni, jit, initial_regs, 5, 5);

2
externals/dynarmic/tests/A32/test_arm_disassembler.cpp vendored
View File

@@ -5,7 +5,7 @@
#include <catch.hpp>
#include "frontend/A32/disassembler/disassembler.h"
#include "dynarmic/frontend/A32/disassembler/disassembler.h"
using Dynarmic::A32::DisassembleArm;

316
externals/dynarmic/tests/A32/test_arm_instructions.cpp vendored
View File

@@ -4,10 +4,10 @@
*/
#include <catch.hpp>
#include <dynarmic/A32/a32.h>
#include "A32/testenv.h"
#include "frontend/A32/location_descriptor.h"
#include "./testenv.h"
#include "dynarmic/frontend/A32/location_descriptor.h"
#include "dynarmic/interface/A32/a32.h"
using namespace Dynarmic;
@@ -27,15 +27,15 @@ TEST_CASE("arm: Opt Failure: Const folding in MostSignificantWord", "[arm][A32]"
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe30ad071, // movw, sp, #41073
0xe75efd3d, // smmulr lr, sp, sp
0xa637af1e, // shadd16ge r10, r7, lr
0xf57ff01f, // clrex
0x86b98879, // sxtahhi r8, r9, r9, ror #16
0xeafffffe, // b +#0
0xe30ad071, // movw, sp, #41073
0xe75efd3d, // smmulr lr, sp, sp
0xa637af1e, // shadd16ge r10, r7, lr
0xf57ff01f, // clrex
0x86b98879, // sxtahhi r8, r9, r9, ror #16
0xeafffffe, // b +#0
};
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 6;
jit.Run();
@@ -69,19 +69,18 @@ TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe35f0cd9, // cmp pc, #55552
0xe11c0474, // tst r12, r4, ror r4
0xe1a006a7, // mov r0, r7, lsr #13
0xe35107fa, // cmp r1, #0x3E80000
0xe2a54c8a, // adc r4, r5, #35328
0xeafffffe, // b +#0
0xe35f0cd9, // cmp pc, #55552
0xe11c0474, // tst r12, r4, ror r4
0xe1a006a7, // mov r0, r7, lsr #13
0xe35107fa, // cmp r1, #0x3E80000
0xe2a54c8a, // adc r4, r5, #35328
0xeafffffe, // b +#0
};
jit.Regs() = {
0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5,
0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0
};
jit.SetCpsr(0x000001d0); // User-mode
0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5,
0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0};
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 6;
jit.Run();
@@ -105,7 +104,7 @@ TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") {
REQUIRE(jit.Cpsr() == 0x200001d0);
}
TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) {
TEST_CASE("arm: shsax (Edge-case)", "[arm][A32]") {
// This was a randomized test-case that was failing.
//
// The issue here was one of the words to be subtracted was 0x8000.
@@ -114,15 +113,14 @@ TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe63dbf59, // shsax r11, sp, r9
0xeafffffe, // b +#0
0xe63dbf59, // shsax r11, sp, r9
0xeafffffe, // b +#0
};
jit.Regs() = {
0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded,
0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000
};
jit.SetCpsr(0x000001d0); // User-mode
0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded,
0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000};
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 2;
jit.Run();
@@ -146,7 +144,7 @@ TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) {
REQUIRE(jit.Cpsr() == 0x000001d0);
}
TEST_CASE( "arm: uasx (Edge-case)", "[arm][A32]" ) {
TEST_CASE("arm: uasx (Edge-case)", "[arm][A32]") {
// UASX's Rm<31:16> == 0x0000.
// An implementation that depends on addition overflow to detect
// if diff >= 0 will fail this testcase.
@@ -154,14 +152,14 @@ TEST_CASE( "arm: uasx (Edge-case)", "[arm][A32]" ) {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe6549f35, // uasx r9, r4, r5
0xeafffffe, // b +#0
0xe6549f35, // uasx r9, r4, r5
0xeafffffe, // b +#0
};
jit.Regs()[4] = 0x8ed38f4c;
jit.Regs()[5] = 0x0000261d;
jit.Regs()[15] = 0x00000000;
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 2;
jit.Run();
@@ -177,20 +175,29 @@ TEST_CASE("arm: smuad (Edge-case)", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xE700F211, // smuad r0, r1, r2
0xeafffffe, // b +#0
0xE700F211, // smuad r0, r1, r2
0xeafffffe, // b +#0
};
jit.Regs() = {
0, // Rd
0x80008000, // Rn
0x80008000, // Rm
0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, // Rd
0x80008000, // Rn
0x80008000, // Rm
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
};
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 2;
jit.Run();
@@ -205,14 +212,14 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe3a00005, // mov r0, #5
0xe3a0100D, // mov r1, #13
0xe0812000, // add r2, r1, r0
0xeafffffe, // b +#0 (infinite loop)
0xe3a00005, // mov r0, #5
0xe3a0100D, // mov r1, #13
0xe0812000, // add r2, r1, r0
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs() = {};
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 4;
jit.Run();
@@ -224,7 +231,7 @@ TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") {
REQUIRE(jit.Cpsr() == 0x000001d0);
// Change the code
test_env.code_mem[1] = 0xe3a01007; // mov r1, #7
test_env.code_mem[1] = 0xe3a01007; // mov r1, #7
jit.InvalidateCacheRange(/*start_memory_location = */ 4, /* length_in_bytes = */ 4);
// Reset position of PC
@@ -246,18 +253,18 @@ TEST_CASE("arm: Step blx", "[arm]") {
config.optimizations |= OptimizationFlag::FastDispatch;
Dynarmic::A32::Jit jit{config};
test_env.code_mem = {
0xe12fff30, // blx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
0xe12fff30, // blx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs()[0] = 8;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 10;
jit.Step();
@@ -274,18 +281,18 @@ TEST_CASE("arm: Step bx", "[arm]") {
config.optimizations |= OptimizationFlag::FastDispatch;
Dynarmic::A32::Jit jit{config};
test_env.code_mem = {
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs()[0] = 8;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 10;
jit.Step();
@@ -295,41 +302,40 @@ TEST_CASE("arm: Step bx", "[arm]") {
REQUIRE(jit.Cpsr() == 0x000001d0);
}
TEST_CASE("arm: Test stepping", "[arm]") {
ArmTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs()[0] = 8;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
for (size_t i = 0; i < 5; ++i) {
test_env.ticks_left = 10;
@@ -350,36 +356,36 @@ TEST_CASE("arm: Test stepping 2", "[arm]") {
ArmTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs()[0] = 4;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
for (size_t i = 0; i < 5; ++i) {
test_env.ticks_left = 10;
@@ -400,18 +406,18 @@ TEST_CASE("arm: Test stepping 3", "[arm]") {
ArmTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe12fff10, // bx r0
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xe320f000, // nop
0xeafffffe, // b +#0 (infinite loop)
0xeafffffe, // b +#0 (infinite loop)
};
jit.Regs()[0] = 4;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 10;
jit.Step();
@@ -433,14 +439,28 @@ TEST_CASE("arm: PackedAbsDiffSumS8", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0x87414354, // smlsldhi r4, r1, r4, r3
0xe7886412, // usad8a r8, r2, r4, r6
0xeafffffe, // b +#0
0x87414354, // smlsldhi r4, r1, r4, r3
0xe7886412, // usad8a r8, r2, r4, r6
0xeafffffe, // b +#0
};
jit.Regs() = {
0xea85297c, 0x417ad918, 0x64f8b70b, 0xcca0373e, 0xbc722361, 0xc528c69e, 0xca926de8, 0xd665d210,
0xb5650555, 0x4a24b25b, 0xaed44144, 0xe87230b2, 0x98e391de, 0x126efc0c, 0xe591fd11, 0x00000000,
0xea85297c,
0x417ad918,
0x64f8b70b,
0xcca0373e,
0xbc722361,
0xc528c69e,
0xca926de8,
0xd665d210,
0xb5650555,
0x4a24b25b,
0xaed44144,
0xe87230b2,
0x98e391de,
0x126efc0c,
0xe591fd11,
0x00000000,
};
jit.SetCpsr(0xb0000010);
@@ -470,14 +490,14 @@ TEST_CASE("arm: vclt.f32 with zero", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xf3b93628, // vclt.f32 d3, d24, #0
0xeafffffe, // b +#0
0xf3b93628, // vclt.f32 d3, d24, #0
0xeafffffe, // b +#0
};
jit.ExtRegs()[48] = 0x3a87d9f1;
jit.ExtRegs()[49] = 0x80796dc0;
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 2;
jit.Run();
@@ -490,14 +510,14 @@ TEST_CASE("arm: vcvt.s16.f64", "[arm][A32]") {
ArmTestEnv test_env;
A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xeebe8b45, // vcvt.s16.f64 d8, d8, #6
0xeafffffe, // b +#0
0xeebe8b45, // vcvt.s16.f64 d8, d8, #6
0xeafffffe, // b +#0
};
jit.ExtRegs()[16] = 0x9a7110b0;
jit.ExtRegs()[17] = 0xcd78f4e7;
jit.SetCpsr(0x000001d0); // User-mode
jit.SetCpsr(0x000001d0); // User-mode
test_env.ticks_left = 2;
jit.Run();
@@ -505,3 +525,37 @@ TEST_CASE("arm: vcvt.s16.f64", "[arm][A32]") {
REQUIRE(jit.ExtRegs()[16] == 0xffff8000);
REQUIRE(jit.ExtRegs()[17] == 0xffffffff);
}
TEST_CASE("arm: Memory access (fastmem)", "[arm][A32]") {
constexpr size_t address_width = 12;
constexpr size_t memory_size = 1ull << address_width; // 4K
constexpr size_t page_size = 4 * 1024;
constexpr size_t buffer_size = 2 * page_size;
char buffer[buffer_size];
void* buffer_ptr = reinterpret_cast<void*>(buffer);
size_t buffer_size_nconst = buffer_size;
char* backing_memory = reinterpret_cast<char*>(std::align(page_size, memory_size, buffer_ptr, buffer_size_nconst));
A32FastmemTestEnv env{backing_memory};
Dynarmic::A32::UserConfig config{&env};
config.fastmem_pointer = backing_memory;
config.recompile_on_fastmem_failure = false;
config.processor_id = 0;
Dynarmic::A32::Jit jit{config};
memset(backing_memory, 0, memory_size);
memcpy(backing_memory + 0x100, "Lorem ipsum dolor sit amet, consectetur adipiscing elit.", 57);
env.MemoryWrite32(0, 0xE5904000); // LDR R4, [R0]
env.MemoryWrite32(4, 0xE5814000); // STR R4, [R1]
env.MemoryWrite32(8, 0xEAFFFFFE); // B .
jit.Regs()[0] = 0x100;
jit.Regs()[1] = 0x1F0;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x000001d0); // User-mode
env.ticks_left = 3;
jit.Run();
REQUIRE(strncmp(backing_memory + 0x100, backing_memory + 0x1F0, 4) == 0);
}

77
externals/dynarmic/tests/A32/test_thumb_instructions.cpp vendored
View File

@@ -5,10 +5,9 @@
#include <catch.hpp>
#include <dynarmic/A32/a32.h>
#include "common/common_types.h"
#include "testenv.h"
#include "./testenv.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/interface/A32/a32.h"
static Dynarmic::A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
Dynarmic::A32::UserConfig user_config;
@@ -20,14 +19,14 @@ TEST_CASE("thumb: lsls r0, r1, #2", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0x0088, // lsls r0, r1, #2
0xE7FE, // b +#0
0x0088, // lsls r0, r1, #2
0xE7FE, // b +#0
};
jit.Regs()[0] = 1;
jit.Regs()[1] = 2;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
@@ -42,14 +41,14 @@ TEST_CASE("thumb: lsls r0, r1, #31", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0x07C8, // lsls r0, r1, #31
0xE7FE, // b +#0
0x07C8, // lsls r0, r1, #31
0xE7FE, // b +#0
};
jit.Regs()[0] = 1;
jit.Regs()[1] = 0xFFFFFFFF;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
@@ -57,20 +56,20 @@ TEST_CASE("thumb: lsls r0, r1, #31", "[thumb]") {
REQUIRE(jit.Regs()[0] == 0x80000000);
REQUIRE(jit.Regs()[1] == 0xffffffff);
REQUIRE(jit.Regs()[15] == 2);
REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode
REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode
}
TEST_CASE("thumb: revsh r4, r3", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xBADC, // revsh r4, r3
0xE7FE, // b +#0
0xBADC, // revsh r4, r3
0xE7FE, // b +#0
};
jit.Regs()[3] = 0x12345678;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
@@ -78,82 +77,82 @@ TEST_CASE("thumb: revsh r4, r3", "[thumb]") {
REQUIRE(jit.Regs()[3] == 0x12345678);
REQUIRE(jit.Regs()[4] == 0x00007856);
REQUIRE(jit.Regs()[15] == 2);
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
}
TEST_CASE("thumb: ldr r3, [r3, #28]", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0x69DB, // ldr r3, [r3, #28]
0xE7FE, // b +#0
0x69DB, // ldr r3, [r3, #28]
0xE7FE, // b +#0
};
jit.Regs()[3] = 0x12345678;
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
REQUIRE(jit.Regs()[3] == 0x97969594); // Memory location 0x12345694
REQUIRE(jit.Regs()[3] == 0x97969594); // Memory location 0x12345694
REQUIRE(jit.Regs()[15] == 2);
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
}
TEST_CASE("thumb: blx +#67712", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xF010, 0xEC3E, // blx +#67712
0xE7FE // b +#0
0xF010, 0xEC3E, // blx +#67712
0xE7FE // b +#0
};
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
REQUIRE(jit.Regs()[14] == (0x4 | 1));
REQUIRE(jit.Regs()[15] == 0x10880);
REQUIRE(jit.Cpsr() == 0x00000010); // User-mode
REQUIRE(jit.Cpsr() == 0x00000010); // User-mode
}
TEST_CASE("thumb: bl +#234584", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xF039, 0xFA2A, // bl +#234584
0xE7FE // b +#0
0xF039, 0xFA2A, // bl +#234584
0xE7FE // b +#0
};
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
REQUIRE(jit.Regs()[14] == (0x4 | 1));
REQUIRE(jit.Regs()[15] == 0x39458);
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
}
TEST_CASE("thumb: bl -#42", "[thumb]") {
ThumbTestEnv test_env;
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
test_env.code_mem = {
0xF7FF, 0xFFE9, // bl -#42
0xE7FE // b +#0
0xF7FF, 0xFFE9, // bl -#42
0xE7FE // b +#0
};
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
jit.Regs()[15] = 0; // PC = 0
jit.SetCpsr(0x00000030); // Thumb, User-mode
test_env.ticks_left = 1;
jit.Run();
REQUIRE(jit.Regs()[14] == (0x4 | 1));
REQUIRE(jit.Regs()[15] == 0xFFFFFFD6);
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
}

100
externals/dynarmic/tests/A32/testenv.h vendored
View File

@@ -11,12 +11,11 @@
#include <string>
#include <vector>
#include <dynarmic/A32/a32.h>
#include "dynarmic/common/assert.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/interface/A32/a32.h"
#include "common/assert.h"
#include "common/common_types.h"
template <typename InstructionType_, u32 infinite_loop_u32>
template<typename InstructionType_, u32 infinite_loop_u32>
class A32TestEnv final : public Dynarmic::A32::UserCallbacks {
public:
using InstructionType = InstructionType_;
@@ -24,12 +23,12 @@ public:
using ExtRegsArray = std::array<u32, 64>;
#ifdef _MSC_VER
#pragma warning(push)
#pragma warning(disable:4309) // C4309: 'static_cast': truncation of constant value
# pragma warning(push)
# pragma warning(disable : 4309) // C4309: 'static_cast': truncation of constant value
#endif
static constexpr InstructionType infinite_loop = static_cast<InstructionType>(infinite_loop_u32);
#ifdef _MSC_VER
#pragma warning(pop)
# pragma warning(pop)
#endif
u64 ticks_left = 0;
@@ -54,7 +53,7 @@ public:
std::memcpy(&value, &code_mem[vaddr / sizeof(InstructionType)], sizeof(u32));
return value;
}
return infinite_loop_u32; // B .
return infinite_loop_u32; // B .
}
std::uint8_t MemoryRead8(u32 vaddr) override {
@@ -115,3 +114,86 @@ public:
using ArmTestEnv = A32TestEnv<u32, 0xEAFFFFFE>;
using ThumbTestEnv = A32TestEnv<u16, 0xE7FEE7FE>;
class A32FastmemTestEnv final : public Dynarmic::A32::UserCallbacks {
public:
u64 ticks_left = 0;
char* backing_memory = nullptr;
explicit A32FastmemTestEnv(char* addr) : backing_memory(addr) {}
template<typename T>
T read(std::uint32_t vaddr) {
T value;
memcpy(&value, backing_memory + vaddr, sizeof(T));
return value;
}
template<typename T>
void write(std::uint32_t vaddr, const T& value) {
memcpy(backing_memory + vaddr, &value, sizeof(T));
}
std::uint32_t MemoryReadCode(std::uint32_t vaddr) override {
return read<std::uint32_t>(vaddr);
}
std::uint8_t MemoryRead8(std::uint32_t vaddr) override {
return read<std::uint8_t>(vaddr);
}
std::uint16_t MemoryRead16(std::uint32_t vaddr) override {
return read<std::uint16_t>(vaddr);
}
std::uint32_t MemoryRead32(std::uint32_t vaddr) override {
return read<std::uint32_t>(vaddr);
}
std::uint64_t MemoryRead64(std::uint32_t vaddr) override {
return read<std::uint64_t>(vaddr);
}
void MemoryWrite8(std::uint32_t vaddr, std::uint8_t value) override {
write(vaddr, value);
}
void MemoryWrite16(std::uint32_t vaddr, std::uint16_t value) override {
write(vaddr, value);
}
void MemoryWrite32(std::uint32_t vaddr, std::uint32_t value) override {
write(vaddr, value);
}
void MemoryWrite64(std::uint32_t vaddr, std::uint64_t value) override {
write(vaddr, value);
}
bool MemoryWriteExclusive8(std::uint32_t vaddr, std::uint8_t value, [[maybe_unused]] std::uint8_t expected) override {
MemoryWrite8(vaddr, value);
return true;
}
bool MemoryWriteExclusive16(std::uint32_t vaddr, std::uint16_t value, [[maybe_unused]] std::uint16_t expected) override {
MemoryWrite16(vaddr, value);
return true;
}
bool MemoryWriteExclusive32(std::uint32_t vaddr, std::uint32_t value, [[maybe_unused]] std::uint32_t expected) override {
MemoryWrite32(vaddr, value);
return true;
}
bool MemoryWriteExclusive64(std::uint32_t vaddr, std::uint64_t value, [[maybe_unused]] std::uint64_t expected) override {
MemoryWrite64(vaddr, value);
return true;
}
void InterpreterFallback(std::uint32_t pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
void AddTicks(std::uint64_t ticks) override {
if (ticks > ticks_left) {
ticks_left = 0;
return;
}
ticks_left -= ticks;
}
std::uint64_t GetTicksRemaining() override {
return ticks_left;
}
};

376
externals/dynarmic/tests/A64/a64.cpp vendored
View File

@@ -5,10 +5,9 @@
#include <catch.hpp>
#include <dynarmic/exclusive_monitor.h>
#include "common/fp/fpsr.h"
#include "testenv.h"
#include "./testenv.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/interface/exclusive_monitor.h"
using namespace Dynarmic;
@@ -16,8 +15,8 @@ TEST_CASE("A64: ADD", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0);
jit.SetRegister(1, 1);
@@ -33,13 +32,75 @@ TEST_CASE("A64: ADD", "[a64]") {
REQUIRE(jit.GetPC() == 4);
}
TEST_CASE("A64: VQADD", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x6e210c02); // UQADD v2.16b, v0.16b, v1.16b
env.code_mem.emplace_back(0x4e210c03); // SQADD v3.16b, v0.16b, v1.16b
env.code_mem.emplace_back(0x6e610c04); // UQADD v4.8h, v0.8h, v1.8h
env.code_mem.emplace_back(0x4e610c05); // SQADD v5.8h, v0.8h, v1.8h
env.code_mem.emplace_back(0x6ea10c06); // UQADD v6.4s, v0.4s, v1.4s
env.code_mem.emplace_back(0x4ea10c07); // SQADD v7.4s, v0.4s, v1.4s
env.code_mem.emplace_back(0x6ee10c08); // UQADD v8.2d, v0.2d, v1.2d
env.code_mem.emplace_back(0x4ee10c09); // SQADD v9.2d, v0.2d, v1.2d
env.code_mem.emplace_back(0x14000000); // B .
jit.SetVector(0, {0x7F7F7F7F7F7F7F7F, 0x7FFFFFFF7FFF7FFF});
jit.SetVector(1, {0x8010FF00807F0000, 0x8000000080008000});
jit.SetPC(0);
env.ticks_left = 9;
jit.Run();
REQUIRE(jit.GetVector(2) == Vector{0xff8fff7ffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(3) == Vector{0xff7f7e7fff7f7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(4) == Vector{0xff8ffffffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(5) == Vector{0xff8f7e7ffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(6) == Vector{0xff907e7ffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(7) == Vector{0xff907e7ffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(8) == Vector{0xff907e7ffffe7f7f, 0xffffffffffffffff});
REQUIRE(jit.GetVector(9) == Vector{0xff907e7ffffe7f7f, 0xffffffffffffffff});
}
TEST_CASE("A64: VQSUB", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x6e212c02); // UQSUB v2.16b, v0.16b, v1.16b
env.code_mem.emplace_back(0x4e212c03); // SQSUB v3.16b, v0.16b, v1.16b
env.code_mem.emplace_back(0x6e612c04); // UQSUB v4.8h, v0.8h, v1.8h
env.code_mem.emplace_back(0x4e612c05); // SQSUB v5.8h, v0.8h, v1.8h
env.code_mem.emplace_back(0x6ea12c06); // UQSUB v6.4s, v0.4s, v1.4s
env.code_mem.emplace_back(0x4ea12c07); // SQSUB v7.4s, v0.4s, v1.4s
env.code_mem.emplace_back(0x6ee12c08); // UQSUB v8.2d, v0.2d, v1.2d
env.code_mem.emplace_back(0x4ee12c09); // SQSUB v9.2d, v0.2d, v1.2d
env.code_mem.emplace_back(0x14000000); // B .
jit.SetVector(0, {0x8010FF00807F0000, 0x8000000080008000});
jit.SetVector(1, {0x7F7F7F7F7F7F7F7F, 0x7FFFFFFF7FFF7FFF});
jit.SetPC(0);
env.ticks_left = 9;
jit.Run();
REQUIRE(jit.GetVector(2) == Vector{0x0100800001000000, 0x0100000001000100});
REQUIRE(jit.GetVector(3) == Vector{0x8091808180008181, 0x8001010180018001});
REQUIRE(jit.GetVector(4) == Vector{0x00917f8101000000, 0x0001000000010001});
REQUIRE(jit.GetVector(5) == Vector{0x8000800080008081, 0x8000000180008000});
REQUIRE(jit.GetVector(6) == Vector{0x00917f8100ff8081, 0x0000000100010001});
REQUIRE(jit.GetVector(7) == Vector{0x8000000080000000, 0x8000000080000000});
REQUIRE(jit.GetVector(8) == Vector{0x00917f8100ff8081, 0x0000000100010001});
REQUIRE(jit.GetVector(9) == Vector{0x8000000000000000, 0x8000000000000000});
}
TEST_CASE("A64: REV", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xdac00c00); // REV X0, X0
env.code_mem.emplace_back(0x5ac00821); // REV W1, W1
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xdac00c00); // REV X0, X0
env.code_mem.emplace_back(0x5ac00821); // REV W1, W1
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0xaabbccddeeff1100);
jit.SetRegister(1, 0xaabbccdd);
@@ -57,8 +118,8 @@ TEST_CASE("A64: REV32", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xdac00800); // REV32 X0, X0
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xdac00800); // REV32 X0, X0
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0xaabbccddeeff1100);
jit.SetPC(0);
@@ -73,9 +134,9 @@ TEST_CASE("A64: REV16", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xdac00400); // REV16 X0, X0
env.code_mem.emplace_back(0x5ac00421); // REV16 W1, W1
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xdac00400); // REV16 X0, X0
env.code_mem.emplace_back(0x5ac00421); // REV16 W1, W1
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0xaabbccddeeff1100);
jit.SetRegister(1, 0xaabbccdd);
@@ -89,12 +150,126 @@ TEST_CASE("A64: REV16", "[a64]") {
REQUIRE(jit.GetPC() == 8);
}
TEST_CASE("A64: XTN", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x0e212803); // XTN v3.8b, v0.8h
env.code_mem.emplace_back(0x0e612824); // XTN v4.4h, v1.4s
env.code_mem.emplace_back(0x0ea12845); // XTN v5.2s, v2.2d
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(0, {0x3333222211110000, 0x7777666655554444});
jit.SetVector(1, {0x1111111100000000, 0x3333333322222222});
jit.SetVector(2, {0x0000000000000000, 0x1111111111111111});
env.ticks_left = 4;
jit.Run();
REQUIRE(jit.GetVector(3) == Vector{0x7766554433221100, 0x0000000000000000});
REQUIRE(jit.GetVector(4) == Vector{0x3333222211110000, 0x0000000000000000});
REQUIRE(jit.GetVector(5) == Vector{0x1111111100000000, 0x0000000000000000});
}
TEST_CASE("A64: TBL", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x0e000100); // TBL v0.8b, { v8.16b }, v0.8b
env.code_mem.emplace_back(0x4e010101); // TBL v1.16b, { v8.16b }, v1.16b
env.code_mem.emplace_back(0x0e022102); // TBL v2.8b, { v8.16b, v9.16b }, v2.8b
env.code_mem.emplace_back(0x4e032103); // TBL v3.16b, { v8.16b, v9.16b }, v3.16b
env.code_mem.emplace_back(0x0e044104); // TBL v4.8b, { v8.16b, v9.16b, v10.16b }, v4.8b
env.code_mem.emplace_back(0x4e054105); // TBL v5.16b, { v8.16b, v9.16b, v10.16b }, v5.16b
env.code_mem.emplace_back(0x0e066106); // TBL v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v6.8b
env.code_mem.emplace_back(0x4e076107); // TBL v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v7.16b
env.code_mem.emplace_back(0x14000000); // B .
// Indices
// 'FF' intended to test out-of-index
jit.SetVector(0, {0x000102030405'FF'07, 0x08090a0b0c0d0e0f});
jit.SetVector(1, {0x000102030405'FF'07, 0x08090a0b0c0d0e0f});
jit.SetVector(2, {0x100011011202'FF'03, 0x1404150516061707});
jit.SetVector(3, {0x100011011202'FF'03, 0x1404150516061707});
jit.SetVector(4, {0x201000211101'FF'12, 0x0233231303241404});
jit.SetVector(5, {0x201000211101'FF'12, 0x0233231303241404});
jit.SetVector(6, {0x403010004131'FF'01, 0x4232120243332303});
jit.SetVector(7, {0x403010004131'FF'01, 0x4232120243332303});
// Table
jit.SetVector(8, {0x7766554433221100, 0xffeeddccbbaa9988});
jit.SetVector(9, {0xffffffffffffffff, 0xffffffffffffffff});
jit.SetVector(10, {0xeeeeeeeeeeeeeeee, 0xeeeeeeeeeeeeeeee});
jit.SetVector(11, {0xdddddddddddddddd, 0xdddddddddddddddd});
jit.SetPC(0);
env.ticks_left = 9;
jit.Run();
REQUIRE(jit.GetVector(0) == Vector{0x001122334455'00'77, 0x0000000000000000});
REQUIRE(jit.GetVector(1) == Vector{0x001122334455'00'77, 0x8899aabbccddeeff});
REQUIRE(jit.GetVector(2) == Vector{0xff00ff11ff22'00'33, 0x0000000000000000});
REQUIRE(jit.GetVector(3) == Vector{0xff00ff11ff22'00'33, 0xff44ff55ff66ff77});
REQUIRE(jit.GetVector(4) == Vector{0xeeff00eeff11'00'ff, 0x0000000000000000});
REQUIRE(jit.GetVector(5) == Vector{0xeeff00eeff11'00'ff, 0x2200eeff33eeff44});
REQUIRE(jit.GetVector(6) == Vector{0x00ddff0000dd'00'11, 0x0000000000000000});
REQUIRE(jit.GetVector(7) == Vector{0x00ddff0000dd'00'11, 0x00ddff2200ddee33});
}
TEST_CASE("A64: TBX", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x0e001100); // TBX v0.8b, { v8.16b }, v0.8b
env.code_mem.emplace_back(0x4e011101); // TBX v1.16b, { v8.16b }, v1.16b
env.code_mem.emplace_back(0x0e023102); // TBX v2.8b, { v8.16b, v9.16b }, v2.8b
env.code_mem.emplace_back(0x4e033103); // TBX v3.16b, { v8.16b, v9.16b }, v3.16b
env.code_mem.emplace_back(0x0e045104); // TBX v4.8b, { v8.16b, v9.16b, v10.16b }, v4.8b
env.code_mem.emplace_back(0x4e055105); // TBX v5.16b, { v8.16b, v9.16b, v10.16b }, v5.16b
env.code_mem.emplace_back(0x0e067106); // TBX v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v6.8b
env.code_mem.emplace_back(0x4e077107); // TBX v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v7.16b
env.code_mem.emplace_back(0x14000000); // B .
// Indices
// 'FF' intended to test out-of-index
jit.SetVector(0, {0x000102030405'FF'07, 0x08090a0b0c0d0e0f});
jit.SetVector(1, {0x000102030405'FF'07, 0x08090a0b0c0d0e0f});
jit.SetVector(2, {0x100011011202'FF'03, 0x1404150516061707});
jit.SetVector(3, {0x100011011202'FF'03, 0x1404150516061707});
jit.SetVector(4, {0x201000211101'FF'12, 0x0233231303241404});
jit.SetVector(5, {0x201000211101'FF'12, 0x0233231303241404});
jit.SetVector(6, {0x403010004131'FF'01, 0x4232120243332303});
jit.SetVector(7, {0x403010004131'FF'01, 0x4232120243332303});
// Table
jit.SetVector(8, {0x7766554433221100, 0xffeeddccbbaa9988});
jit.SetVector(9, {0xffffffffffffffff, 0xffffffffffffffff});
jit.SetVector(10, {0xeeeeeeeeeeeeeeee, 0xeeeeeeeeeeeeeeee});
jit.SetVector(11, {0xdddddddddddddddd, 0xdddddddddddddddd});
jit.SetPC(0);
env.ticks_left = 9;
jit.Run();
REQUIRE(jit.GetVector(0) == Vector{0x001122334455'FF'77, 0x0000000000000000});
REQUIRE(jit.GetVector(1) == Vector{0x001122334455'FF'77, 0x8899aabbccddeeff});
REQUIRE(jit.GetVector(2) == Vector{0xff00ff11ff22'FF'33, 0x0000000000000000});
REQUIRE(jit.GetVector(3) == Vector{0xff00ff11ff22'FF'33, 0xff44ff55ff66ff77});
REQUIRE(jit.GetVector(4) == Vector{0xeeff00eeff11'FF'ff, 0x0000000000000000});
REQUIRE(jit.GetVector(5) == Vector{0xeeff00eeff11'FF'ff, 0x2233eeff33eeff44});
REQUIRE(jit.GetVector(6) == Vector{0x40ddff0041dd'FF'11, 0x0000000000000000});
REQUIRE(jit.GetVector(7) == Vector{0x40ddff0041dd'FF'11, 0x42ddff2243ddee33});
}
TEST_CASE("A64: AND", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x8a020020); // AND X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x8a020020); // AND X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
jit.SetRegister(0, 0);
jit.SetRegister(1, 1);
@@ -114,10 +289,10 @@ TEST_CASE("A64: Bitmasks", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x3200c3e0); // ORR W0, WZR, #0x01010101
env.code_mem.emplace_back(0x320c8fe1); // ORR W1, WZR, #0x00F000F0
env.code_mem.emplace_back(0x320003e2); // ORR W2, WZR, #1
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x3200c3e0); // ORR W0, WZR, #0x01010101
env.code_mem.emplace_back(0x320c8fe1); // ORR W1, WZR, #0x00F000F0
env.code_mem.emplace_back(0x320003e2); // ORR W2, WZR, #1
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
@@ -134,8 +309,8 @@ TEST_CASE("A64: ANDS NZCV", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x6a020020); // ANDS W0, W1, W2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x6a020020); // ANDS W0, W1, W2
env.code_mem.emplace_back(0x14000000); // B .
SECTION("N=1, Z=0") {
jit.SetRegister(0, 0);
@@ -189,11 +364,11 @@ TEST_CASE("A64: CBZ", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x34000060); // 0x00 : CBZ X0, label
env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1
env.code_mem.emplace_back(0x14000000); // 0x08 : B.
env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2
env.code_mem.emplace_back(0x14000000); // 0x10 : B .
env.code_mem.emplace_back(0x34000060); // 0x00 : CBZ X0, label
env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1
env.code_mem.emplace_back(0x14000000); // 0x08 : B.
env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2
env.code_mem.emplace_back(0x14000000); // 0x10 : B .
SECTION("no branch") {
jit.SetPC(0);
@@ -222,11 +397,11 @@ TEST_CASE("A64: TBZ", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x36180060); // 0x00 : TBZ X0, 3, label
env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1
env.code_mem.emplace_back(0x14000000); // 0x08 : B .
env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2
env.code_mem.emplace_back(0x14000000); // 0x10 : B .
env.code_mem.emplace_back(0x36180060); // 0x00 : TBZ X0, 3, label
env.code_mem.emplace_back(0x320003e2); // 0x04 : MOV X2, 1
env.code_mem.emplace_back(0x14000000); // 0x08 : B .
env.code_mem.emplace_back(0x321f03e2); // 0x0C : label: MOV X2, 2
env.code_mem.emplace_back(0x14000000); // 0x10 : B .
SECTION("no branch") {
jit.SetPC(0);
@@ -266,8 +441,8 @@ TEST_CASE("A64: FABD", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x6eb5d556); // FABD.4S V22, V10, V21
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x6eb5d556); // FABD.4S V22, V10, V21
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(10, {0xb4858ac77ff39a87, 0x9fce5e14c4873176});
@@ -293,9 +468,9 @@ TEST_CASE("A64: 128-bit exclusive read/write", "[a64]") {
A64::Jit jit{conf};
env.code_mem.emplace_back(0xc87f0861); // LDXP X1, X2, [X3]
env.code_mem.emplace_back(0xc8241865); // STXP W4, X5, X6, [X3]
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xc87f0861); // LDXP X1, X2, [X3]
env.code_mem.emplace_back(0xc8241865); // STXP W4, X5, X6, [X3]
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetRegister(3, 0x1234567812345678);
@@ -317,16 +492,16 @@ TEST_CASE("A64: CNTPCT_EL0", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xd53be021); // MRS X1, CNTPCT_EL0
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd53be022); // MRS X2, CNTPCT_EL0
env.code_mem.emplace_back(0xcb010043); // SUB X3, X2, X1
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xd53be021); // MRS X1, CNTPCT_EL0
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd503201f); // NOP
env.code_mem.emplace_back(0xd53be022); // MRS X2, CNTPCT_EL0
env.code_mem.emplace_back(0xcb010043); // SUB X3, X2, X1
env.code_mem.emplace_back(0x14000000); // B .
env.ticks_left = 10;
jit.Run();
@@ -338,8 +513,8 @@ TEST_CASE("A64: FNMSUB 1", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x1f618a9c); // FNMSUB D28, D20, D1, D2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x1f618a9c); // FNMSUB D28, D20, D1, D2
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(20, {0xe73a51346164bd6c, 0x8080000000002b94});
@@ -356,8 +531,8 @@ TEST_CASE("A64: FNMSUB 2", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x1f2ab88e); // FNMSUB S14, S4, S10, S14
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x1f2ab88e); // FNMSUB S14, S4, S10, S14
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(4, {0x3c9623b101398437, 0x7ff0abcd0ba98d27});
@@ -375,8 +550,8 @@ TEST_CASE("A64: FMADD", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x1f5e0e4a); // FMADD D10, D18, D30, D3
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x1f5e0e4a); // FMADD D10, D18, D30, D3
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(18, {0x8000007600800000, 0x7ff812347f800000});
@@ -394,8 +569,8 @@ TEST_CASE("A64: FMLA.4S (denormal)", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x4e2fcccc); // FMLA.4S V12, V6, V15
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x4e2fcccc); // FMLA.4S V12, V6, V15
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(12, {0x3c9623b17ff80000, 0xbff0000080000076});
@@ -413,8 +588,8 @@ TEST_CASE("A64: FMLA.4S (0x80800000)", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x4e38cc2b); // FMLA.4S V11, V1, V24
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x4e38cc2b); // FMLA.4S V11, V1, V24
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(11, {0xc79b271efff05678, 0xffc0000080800000});
@@ -435,8 +610,8 @@ TEST_CASE("A64: FMADD (0x80800000)", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x1f0f7319); // FMADD S25, S24, S15, S28
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x1f0f7319); // FMADD S25, S24, S15, S28
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(24, {0x00800000, 0});
@@ -454,9 +629,9 @@ TEST_CASE("A64: FNEG failed to zero upper", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x2ea0fb50); // FNEG.2S V16, V26
env.code_mem.emplace_back(0x2e207a1c); // SQNEG.8B V28, V16
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x2ea0fb50); // FNEG.2S V16, V26
env.code_mem.emplace_back(0x2e207a1c); // SQNEG.8B V28, V16
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetVector(26, {0x071286fde8f34a90, 0x837cffa8be382f60});
@@ -473,8 +648,8 @@ TEST_CASE("A64: FRSQRTS", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x5eb8fcad); // FRSQRTS S13, S5, S24
env.code_mem.emplace_back(0x14000000); // B .
// These particular values result in an intermediate value during
// the calculation that is close to infinity. We want to verify
@@ -495,8 +670,8 @@ TEST_CASE("A64: SQDMULH.8H (saturate)", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x4e62b420); // SQDMULH.8H V0, V1, V2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x4e62b420); // SQDMULH.8H V0, V1, V2
env.code_mem.emplace_back(0x14000000); // B .
// Make sure that saturating values are tested
@@ -516,8 +691,8 @@ TEST_CASE("A64: SQDMULH.4S (saturate)", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0x4ea2b420); // SQDMULH.4S V0, V1, V2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x4ea2b420); // SQDMULH.4S V0, V1, V2
env.code_mem.emplace_back(0x14000000); // B .
// Make sure that saturating values are tested
@@ -543,8 +718,8 @@ TEST_CASE("A64: This is an infinite loop if fast dispatch is enabled", "[a64]")
env.code_mem.emplace_back(0x2ef41c11);
env.code_mem.emplace_back(0x0f07fdd8);
env.code_mem.emplace_back(0x9ac90d09);
env.code_mem.emplace_back(0xd63f0120); // BLR X9
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xd63f0120); // BLR X9
env.code_mem.emplace_back(0x14000000); // B .
env.ticks_left = 6;
jit.Run();
@@ -554,12 +729,12 @@ TEST_CASE("A64: Optimization failure when folding ADD", "[a64]") {
A64TestEnv env;
A64::Jit jit{A64::UserConfig{&env}};
env.code_mem.emplace_back(0xbc4f84be); // LDR S30, [X5], #248
env.code_mem.emplace_back(0x9a0c00ea); // ADC X10, X7, X12
env.code_mem.emplace_back(0x5a1a0079); // SBC W25, W3, W26
env.code_mem.emplace_back(0x9b0e2be9); // MADD X9, XZR, X14, X10
env.code_mem.emplace_back(0xfa5fe8a9); // CCMP X5, #31, #9, AL
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xbc4f84be); // LDR S30, [X5], #248
env.code_mem.emplace_back(0x9a0c00ea); // ADC X10, X7, X12
env.code_mem.emplace_back(0x5a1a0079); // SBC W25, W3, W26
env.code_mem.emplace_back(0x9b0e2be9); // MADD X9, XZR, X14, X10
env.code_mem.emplace_back(0xfa5fe8a9); // CCMP X5, #31, #9, AL
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetRegister(0, 0x46e15845dba57924);
@@ -655,10 +830,53 @@ TEST_CASE("A64: Cache Maintenance Instructions", "[a64]") {
jit.SetRegister(0, 0xcafed00d);
jit.SetRegister(1, 0xcafebabe);
env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0
env.code_mem.emplace_back(0xd5087621); // dc ivac, x1
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xd50b7520); // ic ivau, x0
env.code_mem.emplace_back(0xd5087621); // dc ivac, x1
env.code_mem.emplace_back(0x14000000); // B .
env.ticks_left = 3;
jit.Run();
}
TEST_CASE("A64: Memory access (fastmem)", "[a64]") {
constexpr size_t address_width = 12;
constexpr size_t memory_size = 1ull << address_width; // 4K
constexpr size_t page_size = 4 * 1024;
constexpr size_t buffer_size = 2 * page_size;
char buffer[buffer_size];
void* buffer_ptr = reinterpret_cast<void*>(buffer);
size_t buffer_size_nconst = buffer_size;
char* backing_memory = reinterpret_cast<char*>(std::align(page_size, memory_size, buffer_ptr, buffer_size_nconst));
A64FastmemTestEnv env{backing_memory};
Dynarmic::A64::UserConfig config{&env};
config.fastmem_pointer = backing_memory;
config.page_table_address_space_bits = address_width;
config.recompile_on_fastmem_failure = false;
config.silently_mirror_page_table = true;
config.processor_id = 0;
Dynarmic::A64::Jit jit{config};
memset(backing_memory, 0, memory_size);
memcpy(backing_memory + 0x100, "Lorem ipsum dolor sit amet, consectetur adipiscing elit.", 57);
env.MemoryWrite32(0, 0xA9401404); // LDP X4, X5, [X0]
env.MemoryWrite32(4, 0xF9400046); // LDR X6, [X2]
env.MemoryWrite32(8, 0xA9001424); // STP X4, X5, [X1]
env.MemoryWrite32(12, 0xF9000066); // STR X6, [X3]
env.MemoryWrite32(16, 0x14000000); // B .
jit.SetRegister(0, 0x100);
jit.SetRegister(1, 0x1F0);
jit.SetRegister(2, 0x10F);
jit.SetRegister(3, 0x1FF);
jit.SetPC(0);
jit.SetSP(memory_size - 1);
jit.SetFpsr(0x03480000);
jit.SetPstate(0x30000000);
env.ticks_left = 5;
jit.Run();
REQUIRE(strncmp(backing_memory + 0x100, backing_memory + 0x1F0, 23) == 0);
}

188
externals/dynarmic/tests/A64/fuzz_with_unicorn.cpp vendored
View File

@@ -10,22 +10,22 @@
#include <catch.hpp>
#include "common/common_types.h"
#include "common/fp/fpcr.h"
#include "common/fp/fpsr.h"
#include "common/llvm_disassemble.h"
#include "common/scope_exit.h"
#include "frontend/A64/decoder/a64.h"
#include "frontend/A64/location_descriptor.h"
#include "frontend/A64/translate/translate.h"
#include "frontend/A64/types.h"
#include "frontend/ir/basic_block.h"
#include "frontend/ir/opcodes.h"
#include "fuzz_util.h"
#include "ir_opt/passes.h"
#include "rand_int.h"
#include "testenv.h"
#include "unicorn_emu/a64_unicorn.h"
#include "../fuzz_util.h"
#include "../rand_int.h"
#include "../unicorn_emu/a64_unicorn.h"
#include "./testenv.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/llvm_disassemble.h"
#include "dynarmic/common/scope_exit.h"
#include "dynarmic/frontend/A64/decoder/a64.h"
#include "dynarmic/frontend/A64/location_descriptor.h"
#include "dynarmic/frontend/A64/translate/translate.h"
#include "dynarmic/frontend/A64/types.h"
#include "dynarmic/ir/basic_block.h"
#include "dynarmic/ir/opcodes.h"
#include "dynarmic/ir/opt/passes.h"
// Must be declared last for all necessary operator<< to be declared prior to this.
#include <fmt/format.h>
@@ -59,10 +59,10 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) {
static const struct InstructionGeneratorInfo {
std::vector<InstructionGenerator> generators;
std::vector<InstructionGenerator> invalid;
} instructions = []{
const std::vector<std::tuple<std::string, const char*>> list {
} instructions = [] {
const std::vector<std::tuple<std::string, const char*>> list{
#define INST(fn, name, bitstring) {#fn, bitstring},
#include "frontend/A64/decoder/a64.inc"
#include "dynarmic/frontend/A64/decoder/a64.inc"
#undef INST
};
@@ -70,15 +70,24 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) {
std::vector<InstructionGenerator> invalid;
// List of instructions not to test
const std::vector<std::string> do_not_test {
const std::vector<std::string> do_not_test{
// Unimplemented in QEMU
"STLLR",
// Unimplemented in QEMU
"LDLAR",
// Dynarmic and QEMU currently differ on how the exclusive monitor's address range works.
"STXR", "STLXR", "STXP", "STLXP", "LDXR", "LDAXR", "LDXP", "LDAXP",
"STXR",
"STLXR",
"STXP",
"STLXP",
"LDXR",
"LDAXR",
"LDXP",
"LDAXP",
// Behaviour differs from QEMU
"MSR_reg", "MSR_imm", "MRS",
"MSR_reg",
"MSR_imm",
"MRS",
};
for (const auto& [fn, bitstring] : list) {
@@ -108,16 +117,15 @@ static u32 GenRandomInst(u64 pc, bool is_last_inst) {
}
static u32 GenFloatInst(u64 pc, bool is_last_inst) {
static const std::vector<InstructionGenerator> instruction_generators = []{
const std::vector<std::tuple<std::string, std::string, const char*>> list {
static const std::vector<InstructionGenerator> instruction_generators = [] {
const std::vector<std::tuple<std::string, std::string, const char*>> list{
#define INST(fn, name, bitstring) {#fn, #name, bitstring},
#include "frontend/A64/decoder/a64.inc"
#include "dynarmic/frontend/A64/decoder/a64.inc"
#undef INST
};
// List of instructions not to test
const std::vector<std::string> do_not_test {
};
const std::vector<std::string> do_not_test{};
std::vector<InstructionGenerator> result;
@@ -139,7 +147,7 @@ static u32 GenFloatInst(u64 pc, bool is_last_inst) {
const size_t index = RandInt<size_t>(0, instruction_generators.size() - 1);
const u32 instruction = instruction_generators[index].Generate();
if ((instruction & 0x00800000) == 0 && ShouldTestInst(instruction, pc, is_last_inst)) {
if (ShouldTestInst(instruction, pc, is_last_inst)) {
return instruction;
}
}
@@ -154,13 +162,11 @@ static Dynarmic::A64::UserConfig GetUserConfig(A64TestEnv& jit_env) {
return jit_user_config;
}
static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv& jit_env, A64TestEnv& uni_env,
const A64Unicorn::RegisterArray& regs, const A64Unicorn::VectorArray& vecs, const size_t instructions_start,
const std::vector<u32>& instructions, const u32 pstate, const u32 fpcr) {
static void RunTestInstance(Dynarmic::A64::Jit& jit, A64Unicorn& uni, A64TestEnv& jit_env, A64TestEnv& uni_env, const A64Unicorn::RegisterArray& regs, const A64Unicorn::VectorArray& vecs, const size_t instructions_start, const std::vector<u32>& instructions, const u32 pstate, const u32 fpcr) {
jit_env.code_mem = instructions;
uni_env.code_mem = instructions;
jit_env.code_mem.emplace_back(0x14000000); // B .
uni_env.code_mem.emplace_back(0x14000000); // B .
jit_env.code_mem.emplace_back(0x14000000); // B .
uni_env.code_mem.emplace_back(0x14000000); // B .
jit_env.code_mem_start_address = instructions_start;
uni_env.code_mem_start_address = instructions_start;
jit_env.modified_memory.clear();
@@ -302,7 +308,7 @@ TEST_CASE("A64: Single random instruction", "[a64]") {
std::vector<u32> instructions(1);
for (size_t iteration = 0; iteration < 100000; ++iteration) {
std::generate(regs.begin(), regs.end(), []{ return RandInt<u64>(0, ~u64(0)); });
std::generate(regs.begin(), regs.end(), [] { return RandInt<u64>(0, ~u64(0)); });
std::generate(vecs.begin(), vecs.end(), RandomVector);
instructions[0] = GenRandomInst(0, true);
@@ -324,49 +330,49 @@ TEST_CASE("A64: Floating point instructions", "[a64]") {
Dynarmic::A64::Jit jit{GetUserConfig(jit_env)};
A64Unicorn uni{uni_env};
static constexpr std::array<u64, 80> float_numbers {
0x00000000, // positive zero
0x00000001, // smallest positive denormal
0x00000076, //
0x00002b94, //
0x00636d24, //
0x007fffff, // largest positive denormal
0x00800000, // smallest positive normalised real
0x00800002, //
0x01398437, //
0x0ba98d27, //
0x0ba98d7a, //
0x751f853a, //
0x7f7ffff0, //
0x7f7fffff, // largest positive normalised real
0x7f800000, // positive infinity
0x7f800001, // first positive SNaN
0x7f984a37, //
0x7fbfffff, // last positive SNaN
0x7fc00000, // first positive QNaN
0x7fd9ba98, //
0x7fffffff, // last positive QNaN
0x80000000, // negative zero
0x80000001, // smallest negative denormal
0x80000076, //
0x80002b94, //
0x80636d24, //
0x807fffff, // largest negative denormal
0x80800000, // smallest negative normalised real
0x80800002, //
0x81398437, //
0x8ba98d27, //
0x8ba98d7a, //
0xf51f853a, //
0xff7ffff0, //
0xff7fffff, // largest negative normalised real
0xff800000, // negative infinity
0xff800001, // first negative SNaN
0xff984a37, //
0xffbfffff, // last negative SNaN
0xffc00000, // first negative QNaN
0xffd9ba98, //
0xffffffff, // last negative QNaN
static constexpr std::array<u64, 80> float_numbers{
0x00000000, // positive zero
0x00000001, // smallest positive denormal
0x00000076, //
0x00002b94, //
0x00636d24, //
0x007fffff, // largest positive denormal
0x00800000, // smallest positive normalised real
0x00800002, //
0x01398437, //
0x0ba98d27, //
0x0ba98d7a, //
0x751f853a, //
0x7f7ffff0, //
0x7f7fffff, // largest positive normalised real
0x7f800000, // positive infinity
0x7f800001, // first positive SNaN
0x7f984a37, //
0x7fbfffff, // last positive SNaN
0x7fc00000, // first positive QNaN
0x7fd9ba98, //
0x7fffffff, // last positive QNaN
0x80000000, // negative zero
0x80000001, // smallest negative denormal
0x80000076, //
0x80002b94, //
0x80636d24, //
0x807fffff, // largest negative denormal
0x80800000, // smallest negative normalised real
0x80800002, //
0x81398437, //
0x8ba98d27, //
0x8ba98d7a, //
0xf51f853a, //
0xff7ffff0, //
0xff7fffff, // largest negative normalised real
0xff800000, // negative infinity
0xff800001, // first negative SNaN
0xff984a37, //
0xffbfffff, // last negative SNaN
0xffc00000, // first negative QNaN
0xffd9ba98, //
0xffffffff, // last negative QNaN
// some random numbers follow
0x4f3495cb,
0xe73a5134,
@@ -397,23 +403,26 @@ TEST_CASE("A64: Floating point instructions", "[a64]") {
0xc79b271e,
0x460e8c84,
// some 64-bit-float upper-halves
0x7ff00000, // +SNaN / +Inf
0x7ff0abcd, // +SNaN
0x7ff80000, // +QNaN
0x7ff81234, // +QNaN
0xfff00000, // -SNaN / -Inf
0xfff05678, // -SNaN
0xfff80000, // -QNaN
0xfff809ef, // -QNaN
0x3ff00000, // Number near +1.0
0xbff00000, // Number near -1.0
0x7ff00000, // +SNaN / +Inf
0x7ff0abcd, // +SNaN
0x7ff80000, // +QNaN
0x7ff81234, // +QNaN
0xfff00000, // -SNaN / -Inf
0xfff05678, // -SNaN
0xfff80000, // -QNaN
0xfff809ef, // -QNaN
0x3ff00000, // Number near +1.0
0xbff00000, // Number near -1.0
};
const auto gen_float = [&]{
const auto gen_float = [&] {
if (RandInt<size_t>(0, 1) == 0) {
return RandInt<u64>(0, 0xffffffff);
}
return float_numbers[RandInt<size_t>(0, float_numbers.size() - 1)];
};
const auto gen_vector = [&]{
const auto gen_vector = [&] {
u64 upper = (gen_float() << 32) | gen_float();
u64 lower = (gen_float() << 32) | gen_float();
return Vector{lower, upper};
@@ -474,7 +483,6 @@ TEST_CASE("A64: Small random block", "[a64]") {
}
}
TEST_CASE("A64: Large random block", "[a64]") {
A64TestEnv jit_env{};
A64TestEnv uni_env{};

9
externals/dynarmic/tests/A64/misaligned_page_table.cpp vendored
View File

@@ -5,9 +5,8 @@
#include <catch.hpp>
#include <dynarmic/A64/a64.h>
#include "testenv.h"
#include "./testenv.h"
#include "dynarmic/interface/A64/a64.h"
TEST_CASE("misaligned load/store do not use page_table when detect_misaligned_access_via_page_table is set", "[a64]") {
A64TestEnv env;
@@ -17,8 +16,8 @@ TEST_CASE("misaligned load/store do not use page_table when detect_misaligned_ac
conf.only_detect_misalignment_via_page_table_on_page_boundary = true;
Dynarmic::A64::Jit jit{conf};
env.code_mem.emplace_back(0x3c800400); // STR Q0, [X0], #0
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x3c800400); // STR Q0, [X0], #0
env.code_mem.emplace_back(0x14000000); // B .
jit.SetPC(0);
jit.SetRegister(0, 0x000000000b0afff8);

105
externals/dynarmic/tests/A64/testenv.h vendored
View File

@@ -8,10 +8,9 @@
#include <array>
#include <map>
#include <dynarmic/A64/a64.h>
#include "common/assert.h"
#include "common/common_types.h"
#include "dynarmic/common/assert.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/interface/A64/a64.h"
using Vector = Dynarmic::A64::Vector;
@@ -32,7 +31,7 @@ public:
std::uint32_t MemoryReadCode(u64 vaddr) override {
if (!IsInCodeMem(vaddr)) {
return 0x14000000; // B .
return 0x14000000; // B .
}
const size_t index = (vaddr - code_mem_start_address) / 4;
@@ -125,3 +124,99 @@ public:
return 0x10000000000 - ticks_left;
}
};
class A64FastmemTestEnv final : public Dynarmic::A64::UserCallbacks {
public:
u64 ticks_left = 0;
char* backing_memory = nullptr;
explicit A64FastmemTestEnv(char* addr) : backing_memory(addr) {}
template<typename T>
T read(u64 vaddr) {
T value;
memcpy(&value, backing_memory + vaddr, sizeof(T));
return value;
}
template<typename T>
void write(u64 vaddr, const T& value) {
memcpy(backing_memory + vaddr, &value, sizeof(T));
}
std::uint32_t MemoryReadCode(u64 vaddr) override {
return read<std::uint32_t>(vaddr);
}
std::uint8_t MemoryRead8(u64 vaddr) override {
return read<std::uint8_t>(vaddr);
}
std::uint16_t MemoryRead16(u64 vaddr) override {
return read<std::uint16_t>(vaddr);
}
std::uint32_t MemoryRead32(u64 vaddr) override {
return read<std::uint32_t>(vaddr);
}
std::uint64_t MemoryRead64(u64 vaddr) override {
return read<std::uint64_t>(vaddr);
}
Vector MemoryRead128(u64 vaddr) override {
return read<Vector>(vaddr);
}
void MemoryWrite8(u64 vaddr, std::uint8_t value) override {
write(vaddr, value);
}
void MemoryWrite16(u64 vaddr, std::uint16_t value) override {
write(vaddr, value);
}
void MemoryWrite32(u64 vaddr, std::uint32_t value) override {
write(vaddr, value);
}
void MemoryWrite64(u64 vaddr, std::uint64_t value) override {
write(vaddr, value);
}
void MemoryWrite128(u64 vaddr, Vector value) override {
write(vaddr, value);
}
bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, [[maybe_unused]] std::uint8_t expected) override {
MemoryWrite8(vaddr, value);
return true;
}
bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, [[maybe_unused]] std::uint16_t expected) override {
MemoryWrite16(vaddr, value);
return true;
}
bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, [[maybe_unused]] std::uint32_t expected) override {
MemoryWrite32(vaddr, value);
return true;
}
bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, [[maybe_unused]] std::uint64_t expected) override {
MemoryWrite64(vaddr, value);
return true;
}
bool MemoryWriteExclusive128(u64 vaddr, Vector value, [[maybe_unused]] Vector expected) override {
MemoryWrite128(vaddr, value);
return true;
}
void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
void AddTicks(std::uint64_t ticks) override {
if (ticks > ticks_left) {
ticks_left = 0;
return;
}
ticks_left -= ticks;
}
std::uint64_t GetTicksRemaining() override {
return ticks_left;
}
std::uint64_t GetCNTPCT() override {
return 0x10000000000 - ticks_left;
}
};

21
externals/dynarmic/tests/A64/verify_unicorn.cpp vendored
View File

@@ -7,24 +7,23 @@
#include <catch.hpp>
#include "rand_int.h"
#include "testenv.h"
#include "unicorn_emu/a64_unicorn.h"
#include "../rand_int.h"
#include "../unicorn_emu/a64_unicorn.h"
#include "./testenv.h"
using namespace Dynarmic;
TEST_CASE("Unicorn: Sanity test", "[a64]") {
A64TestEnv env;
env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x8b020020); // ADD X0, X1, X2
env.code_mem.emplace_back(0x14000000); // B .
constexpr A64Unicorn::RegisterArray regs{
0, 1, 2, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0
};
0, 0, 0, 0, 0, 0, 0};
A64Unicorn unicorn{env};
@@ -43,8 +42,8 @@ TEST_CASE("Unicorn: Sanity test", "[a64]") {
TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") {
A64TestEnv env;
env.code_mem.emplace_back(0x385fed99); // LDRB W25, [X12, #0xfffffffffffffffe]!
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0x385fed99); // LDRB W25, [X12, #0xfffffffffffffffe]!
env.code_mem.emplace_back(0x14000000); // B .
A64Unicorn::RegisterArray regs{};
regs[12] = 1;
@@ -63,8 +62,8 @@ TEST_CASE("Unicorn: Ensure 0xFFFF'FFFF'FFFF'FFFF is readable", "[a64]") {
TEST_CASE("Unicorn: Ensure is able to read across page boundaries", "[a64]") {
A64TestEnv env;
env.code_mem.emplace_back(0xb85f93d9); // LDUR W25, [X30, #0xfffffffffffffff9]
env.code_mem.emplace_back(0x14000000); // B .
env.code_mem.emplace_back(0xb85f93d9); // LDUR W25, [X30, #0xfffffffffffffff9]
env.code_mem.emplace_back(0x14000000); // B .
A64Unicorn::RegisterArray regs{};
regs[30] = 4;

9
externals/dynarmic/tests/CMakeLists.txt vendored
View File

@@ -19,6 +19,13 @@ add_executable(dynarmic_tests
rand_int.h
)
if (NOT MSVC)
target_sources(dynarmic_tests PRIVATE
rsqrt_test.cpp
rsqrt_test_fn.s
)
endif()
if (DYNARMIC_TESTS_USE_UNICORN)
target_sources(dynarmic_tests PRIVATE
A32/fuzz_arm.cpp
@@ -47,7 +54,7 @@ create_target_directory_groups(dynarmic_print_info)
target_link_libraries(dynarmic_tests PRIVATE dynarmic boost catch fmt mp xbyak)
target_include_directories(dynarmic_tests PRIVATE . ../src)
target_compile_options(dynarmic_tests PRIVATE ${DYNARMIC_CXX_FLAGS})
target_compile_definitions(dynarmic_tests PRIVATE FMT_USE_USER_DEFINED_LITERALS=0)
target_compile_definitions(dynarmic_tests PRIVATE FMT_USE_USER_DEFINED_LITERALS=0 CATCH_CONFIG_ENABLE_BENCHMARKING=1)
target_link_libraries(dynarmic_print_info PRIVATE dynarmic boost catch fmt mp)
target_include_directories(dynarmic_print_info PRIVATE . ../src)

119
externals/dynarmic/tests/cpu_info.cpp vendored
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@@ -7,76 +7,93 @@
#include <utility>
#include <catch.hpp>
#include <fmt/format.h>
#include <xbyak_util.h>
TEST_CASE("Host CPU supports", "[a64]") {
Xbyak::util::Cpu cpu_info;
std::array<uint32_t, 4> cpu_name;
for (uint32_t i = 2; i < 5; ++i) {
cpu_info.getCpuid(0x80000000 | i, cpu_name.data());
std::printf("%.16s", reinterpret_cast<const char*>(cpu_name.data()));
}
std::putchar('\n');
cpu_info.putFamily();
static constexpr std::array types{
std::make_pair(Xbyak::util::Cpu::t3DN, "3DN"),
std::make_pair(Xbyak::util::Cpu::tADX, "ADX"),
std::make_pair(Xbyak::util::Cpu::tAESNI, "AESNI"),
std::make_pair(Xbyak::util::Cpu::tAMD, "AMD"),
std::make_pair(Xbyak::util::Cpu::tAVX, "AVX"),
std::make_pair(Xbyak::util::Cpu::tAVX2, "AVX2"),
std::make_pair(Xbyak::util::Cpu::tAVX512_4FMAPS, "AVX5124FMAPS"),
std::make_pair(Xbyak::util::Cpu::tAVX512_4VNNIW, "AVX5124VNNIW"),
std::make_pair(Xbyak::util::Cpu::tAVX512_BITALG, "AVX512BITALG"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VBMI2, "AVX512VBMI2"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VNNI, "AVX512VNNI"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VPOPCNTDQ, "AVX512VPOPCNTDQ"),
std::make_pair(Xbyak::util::Cpu::tAVX512BW, "AVX512BW"),
std::make_pair(Xbyak::util::Cpu::tAVX512CD, "AVX512CD"),
std::make_pair(Xbyak::util::Cpu::tAVX512DQ, "AVX512DQ"),
std::make_pair(Xbyak::util::Cpu::tAVX512ER, "AVX512ER"),
std::make_pair(Xbyak::util::Cpu::tAVX512F, "AVX512F"),
std::make_pair(Xbyak::util::Cpu::tAVX512IFMA, "AVX512IFMA"),
std::make_pair(Xbyak::util::Cpu::tAVX512PF, "AVX512PF"),
std::make_pair(Xbyak::util::Cpu::tAVX512VBMI, "AVX512VBMI"),
std::make_pair(Xbyak::util::Cpu::tAVX512VL, "AVX512VL"),
std::make_pair(Xbyak::util::Cpu::tBMI1, "BMI1"),
std::make_pair(Xbyak::util::Cpu::tBMI2, "BMI2"),
std::make_pair(Xbyak::util::Cpu::tCMOV, "CMOV"),
std::make_pair(Xbyak::util::Cpu::tE3DN, "E3DN"),
std::make_pair(Xbyak::util::Cpu::tENHANCED_REP, "ENHANCED_REP"),
std::make_pair(Xbyak::util::Cpu::tF16C, "F16C"),
std::make_pair(Xbyak::util::Cpu::tFMA, "FMA"),
std::make_pair(Xbyak::util::Cpu::tGFNI, "GFNI"),
std::make_pair(Xbyak::util::Cpu::tHLE, "HLE"),
std::make_pair(Xbyak::util::Cpu::tINTEL, "INTEL"),
std::make_pair(Xbyak::util::Cpu::tLZCNT, "LZCNT"),
std::make_pair(Xbyak::util::Cpu::tMMX, "MMX"),
std::make_pair(Xbyak::util::Cpu::tMMX2, "MMX2"),
std::make_pair(Xbyak::util::Cpu::tCMOV, "CMOV"),
std::make_pair(Xbyak::util::Cpu::tMOVBE, "MOVBE"),
std::make_pair(Xbyak::util::Cpu::tMPX, "MPX"),
std::make_pair(Xbyak::util::Cpu::tOSXSAVE, "OSXSAVE"),
std::make_pair(Xbyak::util::Cpu::tPCLMULQDQ, "PCLMULQDQ"),
std::make_pair(Xbyak::util::Cpu::tPOPCNT, "POPCNT"),
std::make_pair(Xbyak::util::Cpu::tPREFETCHW, "PREFETCHW"),
std::make_pair(Xbyak::util::Cpu::tPREFETCHWT1, "PREFETCHWT1"),
std::make_pair(Xbyak::util::Cpu::tRDRAND, "RDRAND"),
std::make_pair(Xbyak::util::Cpu::tRDSEED, "RDSEED"),
std::make_pair(Xbyak::util::Cpu::tRDTSCP, "RDTSCP"),
std::make_pair(Xbyak::util::Cpu::tRTM, "RTM"),
std::make_pair(Xbyak::util::Cpu::tSHA, "SHA"),
std::make_pair(Xbyak::util::Cpu::tSMAP, "SMAP"),
std::make_pair(Xbyak::util::Cpu::tSSE, "SSE"),
std::make_pair(Xbyak::util::Cpu::tSSE2, "SSE2"),
std::make_pair(Xbyak::util::Cpu::tSSE3, "SSE3"),
std::make_pair(Xbyak::util::Cpu::tSSSE3, "SSSE3"),
std::make_pair(Xbyak::util::Cpu::tSSE41, "SSE41"),
std::make_pair(Xbyak::util::Cpu::tSSE42, "SSE42"),
std::make_pair(Xbyak::util::Cpu::tPOPCNT, "POPCNT"),
std::make_pair(Xbyak::util::Cpu::tAESNI, "AESNI"),
std::make_pair(Xbyak::util::Cpu::tSSE5, "SSE5"),
std::make_pair(Xbyak::util::Cpu::tOSXSAVE, "OSXSAVE"),
std::make_pair(Xbyak::util::Cpu::tPCLMULQDQ, "PCLMULQDQ"),
std::make_pair(Xbyak::util::Cpu::tAVX, "AVX"),
std::make_pair(Xbyak::util::Cpu::tFMA, "FMA"),
std::make_pair(Xbyak::util::Cpu::t3DN, "3DN"),
std::make_pair(Xbyak::util::Cpu::tE3DN, "E3DN"),
std::make_pair(Xbyak::util::Cpu::tSSE4a, "SSE4a"),
std::make_pair(Xbyak::util::Cpu::tRDTSCP, "RDTSCP"),
std::make_pair(Xbyak::util::Cpu::tAVX2, "AVX2"),
std::make_pair(Xbyak::util::Cpu::tBMI1, "BMI1"),
std::make_pair(Xbyak::util::Cpu::tBMI2, "BMI2"),
std::make_pair(Xbyak::util::Cpu::tLZCNT, "LZCNT"),
std::make_pair(Xbyak::util::Cpu::tINTEL, "INTEL"),
std::make_pair(Xbyak::util::Cpu::tAMD, "AMD"),
std::make_pair(Xbyak::util::Cpu::tENHANCED_REP, "ENHANCED_REP"),
std::make_pair(Xbyak::util::Cpu::tRDRAND, "RDRAND"),
std::make_pair(Xbyak::util::Cpu::tADX, "ADX"),
std::make_pair(Xbyak::util::Cpu::tRDSEED, "RDSEED"),
std::make_pair(Xbyak::util::Cpu::tSMAP, "SMAP"),
std::make_pair(Xbyak::util::Cpu::tHLE, "HLE"),
std::make_pair(Xbyak::util::Cpu::tRTM, "RTM"),
std::make_pair(Xbyak::util::Cpu::tF16C, "F16C"),
std::make_pair(Xbyak::util::Cpu::tMOVBE, "MOVBE"),
std::make_pair(Xbyak::util::Cpu::tAVX512F, "AVX512F"),
std::make_pair(Xbyak::util::Cpu::tAVX512DQ, "AVX512DQ"),
std::make_pair(Xbyak::util::Cpu::tAVX512_IFMA, "AVX512_IFMA"),
std::make_pair(Xbyak::util::Cpu::tAVX512IFMA, "AVX512IFMA"),
std::make_pair(Xbyak::util::Cpu::tAVX512PF, "AVX512PF"),
std::make_pair(Xbyak::util::Cpu::tAVX512ER, "AVX512ER"),
std::make_pair(Xbyak::util::Cpu::tAVX512CD, "AVX512CD"),
std::make_pair(Xbyak::util::Cpu::tAVX512BW, "AVX512BW"),
std::make_pair(Xbyak::util::Cpu::tAVX512VL, "AVX512VL"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VBMI, "AVX512_VBMI"),
std::make_pair(Xbyak::util::Cpu::tAVX512VBMI, "AVX512VBMI"),
std::make_pair(Xbyak::util::Cpu::tAVX512_4VNNIW, "AVX512_4VNNIW"),
std::make_pair(Xbyak::util::Cpu::tAVX512_4FMAPS, "AVX512_4FMAPS"),
std::make_pair(Xbyak::util::Cpu::tPREFETCHWT1, "PREFETCHWT1"),
std::make_pair(Xbyak::util::Cpu::tPREFETCHW, "PREFETCHW"),
std::make_pair(Xbyak::util::Cpu::tSHA, "SHA"),
std::make_pair(Xbyak::util::Cpu::tMPX, "MPX"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VBMI2, "AVX512_VBMI2"),
std::make_pair(Xbyak::util::Cpu::tGFNI, "GFNI"),
std::make_pair(Xbyak::util::Cpu::tSSE5, "SSE5"),
std::make_pair(Xbyak::util::Cpu::tSSSE3, "SSSE3"),
std::make_pair(Xbyak::util::Cpu::tVAES, "VAES"),
std::make_pair(Xbyak::util::Cpu::tVPCLMULQDQ, "VPCLMULQDQ"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VNNI, "AVX512_VNNI"),
std::make_pair(Xbyak::util::Cpu::tAVX512_BITALG, "AVX512_BITALG"),
std::make_pair(Xbyak::util::Cpu::tAVX512_VPOPCNTDQ, "AVX512_VPOPCNTDQ"),
};
constexpr size_t line_max = 80;
size_t line_length = 0;
for (const auto& [type, name] : types) {
if (cpu_info.has(type)) {
fmt::print("CPU has {}\n", name);
const size_t name_length = std::strlen(name) + 1;
if ((line_length + name_length) >= line_max) {
line_length = name_length;
std::putchar('\n');
} else if (line_length) {
std::putchar(' ');
}
std::fputs(name, stdout);
line_length += name_length;
}
}
std::putchar('\n');
}

22
externals/dynarmic/tests/decoder_tests.cpp vendored
View File

@@ -4,34 +4,34 @@
*/
#include <cstring>
#include <iostream>
#include <iomanip>
#include <iostream>
#include <catch.hpp>
#include <dynarmic/A32/config.h>
#include "common/assert.h"
#include "frontend/A32/decoder/asimd.h"
#include "frontend/A32/translate/impl/translate_arm.h"
#include "frontend/ir/opcodes.h"
#include "dynarmic/common/assert.h"
#include "dynarmic/frontend/A32/decoder/asimd.h"
#include "dynarmic/frontend/A32/translate/impl/translate.h"
#include "dynarmic/interface/A32/config.h"
#include "dynarmic/ir/opcodes.h"
using namespace Dynarmic;
TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32]") {
const auto table = A32::GetASIMDDecodeTable<A32::ArmTranslatorVisitor>();
TEST_CASE("ASIMD Decoder: Ensure table order correctness", "[decode][a32][.]") {
const auto table = A32::GetASIMDDecodeTable<A32::TranslatorVisitor>();
const auto get_ir = [](const A32::ASIMDMatcher<A32::ArmTranslatorVisitor>& matcher, u32 instruction) {
const auto get_ir = [](const A32::ASIMDMatcher<A32::TranslatorVisitor>& matcher, u32 instruction) {
ASSERT(matcher.Matches(instruction));
const A32::LocationDescriptor location{0, {}, {}};
IR::Block block{location};
A32::ArmTranslatorVisitor visitor{block, location, {}};
A32::TranslatorVisitor visitor{block, location, {}};
matcher.call(visitor, instruction);
return block;
};
const auto is_decode_error = [&get_ir](const A32::ASIMDMatcher<A32::ArmTranslatorVisitor>& matcher, u32 instruction){
const auto is_decode_error = [&get_ir](const A32::ASIMDMatcher<A32::TranslatorVisitor>& matcher, u32 instruction) {
const auto block = get_ir(matcher, instruction);
for (const auto& ir_inst : block) {

14
externals/dynarmic/tests/fp/FPToFixed.cpp vendored
View File

@@ -8,18 +8,18 @@
#include <catch.hpp>
#include "common/common_types.h"
#include "common/fp/fpcr.h"
#include "common/fp/fpsr.h"
#include "common/fp/op.h"
#include "common/fp/rounding_mode.h"
#include "rand_int.h"
#include "../rand_int.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/op.h"
#include "dynarmic/common/fp/rounding_mode.h"
using namespace Dynarmic;
using namespace Dynarmic::FP;
TEST_CASE("FPToFixed", "[fp]") {
const std::vector<std::tuple<u32, size_t, u64, u32>> test_cases {
const std::vector<std::tuple<u32, size_t, u64, u32>> test_cases{
{0x447A0000, 64, 0x000003E8, 0x00},
{0xC47A0000, 32, 0xFFFFFC18, 0x00},
{0x4479E000, 64, 0x000003E8, 0x10},

2
externals/dynarmic/tests/fp/FPValue.cpp vendored
View File

@@ -3,7 +3,7 @@
* SPDX-License-Identifier: 0BSD
*/
#include "common/fp/info.h"
#include "dynarmic/common/fp/info.h"
using namespace Dynarmic::FP;

12
externals/dynarmic/tests/fp/mantissa_util_tests.cpp vendored
View File

@@ -8,16 +8,16 @@
#include <catch.hpp>
#include "common/common_types.h"
#include "common/fp/mantissa_util.h"
#include "common/safe_ops.h"
#include "rand_int.h"
#include "../rand_int.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/mantissa_util.h"
#include "dynarmic/common/safe_ops.h"
using namespace Dynarmic;
using namespace Dynarmic::FP;
TEST_CASE("ResidualErrorOnRightShift", "[fp]") {
const std::vector<std::tuple<u32, int, ResidualError>> test_cases {
const std::vector<std::tuple<u32, int, ResidualError>> test_cases{
{0x00000001, 1, ResidualError::Half},
{0x00000002, 1, ResidualError::Zero},
{0x00000001, 2, ResidualError::LessThanHalf},
@@ -43,7 +43,7 @@ TEST_CASE("ResidualErrorOnRightShift Randomized", "[fp]") {
const ResidualError result = ResidualErrorOnRightShift(mantissa, shift);
const u64 calculated_error = Safe::ArithmeticShiftRightDouble(mantissa, u64(0), shift);
const ResidualError expected_result = [&]{
const ResidualError expected_result = [&] {
constexpr u64 half_error = 0x8000'0000'0000'0000ull;
if (calculated_error == 0) {
return ResidualError::Zero;

24
externals/dynarmic/tests/fp/unpacked_tests.cpp vendored
View File

@@ -8,17 +8,17 @@
#include <catch.hpp>
#include "common/common_types.h"
#include "common/fp/fpcr.h"
#include "common/fp/fpsr.h"
#include "common/fp/unpacked.h"
#include "rand_int.h"
#include "../rand_int.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/unpacked.h"
using namespace Dynarmic;
using namespace Dynarmic::FP;
TEST_CASE("FPUnpack Tests", "[fp]") {
const static std::vector<std::tuple<u32, std::tuple<FPType, bool, FPUnpacked>, u32>> test_cases {
const static std::vector<std::tuple<u32, std::tuple<FPType, bool, FPUnpacked>, u32>> test_cases{
{0x00000000, {FPType::Zero, false, ToNormalized(false, 0, 0)}, 0},
{0x7F800000, {FPType::Infinity, false, ToNormalized(false, 1000000, 1)}, 0},
{0xFF800000, {FPType::Infinity, true, ToNormalized(true, 1000000, 1)}, 0},
@@ -26,8 +26,8 @@ TEST_CASE("FPUnpack Tests", "[fp]") {
{0xFF800001, {FPType::SNaN, true, ToNormalized(true, 0, 0)}, 0},
{0x7FC00001, {FPType::QNaN, false, ToNormalized(false, 0, 0)}, 0},
{0xFFC00001, {FPType::QNaN, true, ToNormalized(true, 0, 0)}, 0},
{0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149.
{0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon
{0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149.
{0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon
};
const FPCR fpcr;
@@ -49,12 +49,12 @@ TEST_CASE("FPUnpack Tests", "[fp]") {
}
TEST_CASE("FPRound Tests", "[fp]") {
const static std::vector<std::tuple<u32, std::tuple<FPType, bool, FPUnpacked>, u32>> test_cases {
const static std::vector<std::tuple<u32, std::tuple<FPType, bool, FPUnpacked>, u32>> test_cases{
{0x7F800000, {FPType::Infinity, false, ToNormalized(false, 1000000, 1)}, 0x14},
{0xFF800000, {FPType::Infinity, true, ToNormalized(true, 1000000, 1)}, 0x14},
{0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149.
{0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon
{0x3F800000, {FPType::Nonzero, false, ToNormalized(false, -28, 0xFFFFFFF)}, 0x10}, // rounds to 1.0
{0x00000001, {FPType::Nonzero, false, ToNormalized(false, -149, 1)}, 0}, // Smallest single precision denormal is 2^-149.
{0x3F7FFFFF, {FPType::Nonzero, false, ToNormalized(false, -24, 0xFFFFFF)}, 0}, // 1.0 - epsilon
{0x3F800000, {FPType::Nonzero, false, ToNormalized(false, -28, 0xFFFFFFF)}, 0x10}, // rounds to 1.0
};
const FPCR fpcr;

13
externals/dynarmic/tests/fuzz_util.cpp vendored
View File

@@ -3,16 +3,17 @@
* SPDX-License-Identifier: 0BSD
*/
#include "./fuzz_util.h"
#include <cstring>
#include <fmt/format.h>
#include <fmt/ostream.h>
#include "common/assert.h"
#include "common/fp/fpcr.h"
#include "common/fp/rounding_mode.h"
#include "fuzz_util.h"
#include "rand_int.h"
#include "./rand_int.h"
#include "dynarmic/common/assert.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/rounding_mode.h"
using namespace Dynarmic;
@@ -34,7 +35,7 @@ u32 RandomFpcr() {
return fpcr.Value();
}
InstructionGenerator::InstructionGenerator(const char* format){
InstructionGenerator::InstructionGenerator(const char* format) {
const size_t format_len = std::strlen(format);
ASSERT(format_len == 16 || format_len == 32);

2
externals/dynarmic/tests/fuzz_util.h vendored
View File

@@ -8,7 +8,7 @@
#include <array>
#include <iosfwd>
#include "common/common_types.h"
#include "dynarmic/common/common_types.h"
using Vector = std::array<u64, 2>;

93
externals/dynarmic/tests/print_info.cpp vendored
View File

@@ -12,35 +12,35 @@
#include <optional>
#include <string>
#include <dynarmic/A32/a32.h>
#include <dynarmic/A32/disassembler.h>
#include "common/common_types.h"
#include "common/llvm_disassemble.h"
#include "frontend/A32/decoder/arm.h"
#include "frontend/A32/decoder/asimd.h"
#include "frontend/A32/decoder/vfp.h"
#include "frontend/A32/location_descriptor.h"
#include "frontend/A32/translate/impl/translate_arm.h"
#include "frontend/A32/translate/translate.h"
#include "frontend/A64/decoder/a64.h"
#include "frontend/A64/location_descriptor.h"
#include "frontend/A64/translate/impl/impl.h"
#include "frontend/A64/translate/translate.h"
#include "frontend/ir/basic_block.h"
#include "ir_opt/passes.h"
#include <fmt/format.h>
#include <fmt/ostream.h>
#include "dynarmic/common/bit_util.h"
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/llvm_disassemble.h"
#include "dynarmic/frontend/A32/decoder/arm.h"
#include "dynarmic/frontend/A32/decoder/asimd.h"
#include "dynarmic/frontend/A32/decoder/vfp.h"
#include "dynarmic/frontend/A32/location_descriptor.h"
#include "dynarmic/frontend/A32/translate/impl/translate.h"
#include "dynarmic/frontend/A32/translate/translate.h"
#include "dynarmic/frontend/A64/decoder/a64.h"
#include "dynarmic/frontend/A64/location_descriptor.h"
#include "dynarmic/frontend/A64/translate/impl/impl.h"
#include "dynarmic/frontend/A64/translate/translate.h"
#include "dynarmic/interface/A32/a32.h"
#include "dynarmic/interface/A32/disassembler.h"
#include "dynarmic/ir/basic_block.h"
#include "dynarmic/ir/opt/passes.h"
using namespace Dynarmic;
const char* GetNameOfA32Instruction(u32 instruction) {
if (auto vfp_decoder = A32::DecodeVFP<A32::ArmTranslatorVisitor>(instruction)) {
if (auto vfp_decoder = A32::DecodeVFP<A32::TranslatorVisitor>(instruction)) {
return vfp_decoder->get().GetName();
} else if (auto asimd_decoder = A32::DecodeASIMD<A32::ArmTranslatorVisitor>(instruction)) {
} else if (auto asimd_decoder = A32::DecodeASIMD<A32::TranslatorVisitor>(instruction)) {
return asimd_decoder->get().GetName();
} else if (auto decoder = A32::DecodeArm<A32::ArmTranslatorVisitor>(instruction)) {
} else if (auto decoder = A32::DecodeArm<A32::TranslatorVisitor>(instruction)) {
return decoder->get().GetName();
}
return "<null>";
@@ -95,6 +95,30 @@ void PrintA64Instruction(u32 instruction) {
fmt::print("{}\n", IR::DumpBlock(block));
}
void PrintThumbInstruction(u32 instruction) {
const size_t inst_size = (instruction >> 16) == 0 ? 2 : 4;
if (inst_size == 4)
instruction = Common::SwapHalves32(instruction);
fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size));
const A32::LocationDescriptor location{0, A32::PSR{0x1F0}, {}};
IR::Block block{location};
const bool should_continue = A32::TranslateSingleInstruction(block, location, instruction);
fmt::print("should_continue: {}\n\n", should_continue);
fmt::print("IR:\n");
fmt::print("{}\n", IR::DumpBlock(block));
Optimization::A32GetSetElimination(block);
Optimization::DeadCodeElimination(block);
Optimization::ConstantPropagation(block);
Optimization::DeadCodeElimination(block);
Optimization::IdentityRemovalPass(block);
fmt::print("Optimized IR:\n");
fmt::print("{}\n", IR::DumpBlock(block));
}
class ExecEnv final : public Dynarmic::A32::UserCallbacks {
public:
u64 ticks_left = 0;
@@ -164,7 +188,7 @@ void ExecuteA32Instruction(u32 instruction) {
u32 cpsr = 0;
u32 fpscr = 0;
const std::map<std::string, u32*> name_map = [&regs, &ext_regs, &cpsr, &fpscr]{
const std::map<std::string, u32*> name_map = [&regs, &ext_regs, &cpsr, &fpscr] {
std::map<std::string, u32*> name_map;
for (size_t i = 0; i < regs.size(); i++) {
name_map[fmt::format("r{}", i)] = &regs[i];
@@ -180,7 +204,7 @@ void ExecuteA32Instruction(u32 instruction) {
return name_map;
}();
const auto get_line = [](){
const auto get_line = []() {
std::string line;
std::getline(std::cin, line);
std::transform(line.begin(), line.end(), line.begin(), [](unsigned char c) { return static_cast<char>(std::tolower(c)); });
@@ -189,12 +213,15 @@ void ExecuteA32Instruction(u32 instruction) {
const auto get_value = [&get_line]() -> std::optional<u32> {
std::string line = get_line();
if (line.length() > 2 && line[0] == '0' && line[1] == 'x') line = line.substr(2);
if (line.length() > 8) return std::nullopt;
if (line.length() > 2 && line[0] == '0' && line[1] == 'x')
line = line.substr(2);
if (line.length() > 8)
return std::nullopt;
char* endptr;
const u32 value = strtol(line.c_str(), &endptr, 16);
if (line.c_str() + line.length() != endptr) return std::nullopt;
if (line.c_str() + line.length() != endptr)
return std::nullopt;
return value;
};
@@ -230,7 +257,7 @@ void ExecuteA32Instruction(u32 instruction) {
const u32 initial_pc = regs[15];
env.MemoryWrite32(initial_pc + 0, instruction);
env.MemoryWrite32(initial_pc + 4, 0xEAFFFFFE); // B +0
env.MemoryWrite32(initial_pc + 4, 0xEAFFFFFE); // B +0
cpu.Run();
@@ -259,11 +286,11 @@ void ExecuteA32Instruction(u32 instruction) {
int main(int argc, char** argv) {
if (argc < 3 || argc > 4) {
fmt::print("usage: {} <a32/a64> <instruction_in_hex> [-exec]\n", argv[0]);
fmt::print("usage: {} <a32/a64/thumb> <instruction_in_hex> [-exec]\n", argv[0]);
return 1;
}
const char* const hex_instruction = [argv]{
const char* const hex_instruction = [argv] {
if (strlen(argv[2]) > 2 && argv[2][0] == '0' && argv[2][1] == 'x') {
return argv[2] + 2;
}
@@ -281,8 +308,10 @@ int main(int argc, char** argv) {
PrintA32Instruction(instruction);
} else if (strcmp(argv[1], "a64") == 0) {
PrintA64Instruction(instruction);
} else if (strcmp(argv[1], "t32") == 0 || strcmp(argv[1], "t16") == 0 || strcmp(argv[1], "thumb") == 0) {
PrintThumbInstruction(instruction);
} else {
fmt::print("Invalid mode: {}\nValid values: a32, a64\n", argv[1]);
fmt::print("Invalid mode: {}\nValid values: a32, a64, thumb\n", argv[1]);
return 1;
}
@@ -294,8 +323,8 @@ int main(int argc, char** argv) {
if (strcmp(argv[1], "a32") == 0) {
ExecuteA32Instruction(instruction);
} else if (strcmp(argv[1], "a64") == 0) {
fmt::print("Executing a64 code not currently supported\n");
} else {
fmt::print("Executing in this mode not currently supported\n");
return 1;
}
}

2
externals/dynarmic/tests/rand_int.h vendored
View File

@@ -8,7 +8,7 @@
#include <random>
#include <type_traits>
template <typename T>
template<typename T>
T RandInt(T min, T max) {
static_assert(std::is_integral_v<T>, "T must be an integral type.");
static_assert(!std::is_same_v<T, signed char> && !std::is_same_v<T, unsigned char>,

151
externals/dynarmic/tests/rsqrt_test.cpp vendored Executable file
View File

@@ -0,0 +1,151 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2021 MerryMage
* SPDX-License-Identifier: 0BSD
*/
#include <catch.hpp>
#include <fmt/printf.h>
#include "dynarmic/common/common_types.h"
#include "dynarmic/common/fp/fpcr.h"
#include "dynarmic/common/fp/fpsr.h"
#include "dynarmic/common/fp/op/FPRSqrtEstimate.h"
extern "C" u32 rsqrt_inaccurate(u32);
extern "C" u32 rsqrt_full(u32);
extern "C" u32 rsqrt_full_gpr(u32);
extern "C" u32 rsqrt_full_nb(u32);
extern "C" u32 rsqrt_full_nb2(u32);
extern "C" u32 rsqrt_full_nb_gpr(u32);
extern "C" u32 rsqrt_newton(u32);
extern "C" u32 rsqrt_hack(u32);
using namespace Dynarmic;
extern "C" u32 rsqrt_fallback(u32 value) {
FP::FPCR fpcr;
FP::FPSR fpsr;
return FP::FPRSqrtEstimate(value, fpcr, fpsr);
}
extern "C" u32 _rsqrt_fallback(u32 value) {
return rsqrt_fallback(value);
}
void Test(u32 value) {
FP::FPCR fpcr;
FP::FPSR fpsr;
const u32 expect = FP::FPRSqrtEstimate(value, fpcr, fpsr);
const u32 full = rsqrt_full(value);
const u32 full_gpr = rsqrt_full_gpr(value);
const u32 newton = rsqrt_newton(value);
const u32 hack = rsqrt_hack(value);
if (expect != full || expect != full_gpr || expect != newton || expect != hack) {
fmt::print("{:08x} = {:08x} : {:08x} : {:08x} : {:08x} : {:08x}\n", value, expect, full, full_gpr, newton, hack);
REQUIRE(expect == full);
REQUIRE(expect == full_gpr);
REQUIRE(expect == newton);
REQUIRE(expect == hack);
}
}
TEST_CASE("RSqrt Tests", "[fp][.]") {
Test(0x00000000);
Test(0x80000000);
Test(0x7f8b7201);
Test(0x7f800000);
Test(0x7fc00000);
Test(0xff800000);
Test(0xffc00000);
Test(0xff800001);
for (u64 i = 0; i < 0x1'0000'0000; i++) {
const u32 value = static_cast<u32>(i);
Test(value);
}
}
TEST_CASE("Benchmark RSqrt", "[fp][.]") {
BENCHMARK("Inaccurate") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_inaccurate(value);
}
return total;
};
BENCHMARK("Full divss") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_full(value);
}
return total;
};
BENCHMARK("Full divss (GPR)") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_full_gpr(value);
}
return total;
};
BENCHMARK("Full divss (NB)") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_full_nb(value);
}
return total;
};
BENCHMARK("Full divss (NB2)") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_full_nb2(value);
}
return total;
};
BENCHMARK("Full divss (NB + GPR)") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_full_nb_gpr(value);
}
return total;
};
BENCHMARK("One Newton iteration") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_newton(value);
}
return total;
};
BENCHMARK("Ugly Hack") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_hack(value);
}
return total;
};
BENCHMARK("Softfloat") {
u64 total = 0;
for (u64 i = 0; i < 0x1'0000'0000; i += 0x1234) {
const u32 value = static_cast<u32>(i);
total += rsqrt_fallback(value);
}
return total;
};
}

303
externals/dynarmic/tests/rsqrt_test_fn.s vendored Executable file
View File

@@ -0,0 +1,303 @@
.global _rsqrt_inaccurate
.global rsqrt_inaccurate
.global _rsqrt_full
.global rsqrt_full
.global _rsqrt_full_gpr
.global rsqrt_full_gpr
.global _rsqrt_full_nb
.global rsqrt_full_nb
.global _rsqrt_full_nb2
.global rsqrt_full_nb2
.global _rsqrt_full_nb_gpr
.global rsqrt_full_nb_gpr
.global _rsqrt_newton
.global rsqrt_newton
.global _rsqrt_hack
.global rsqrt_hack
.global _rsqrt_fallback
.text
.intel_syntax noprefix
.align 16
min_pos_denorm:
.long 0x00800000,0,0,0
penultimate_bit:
.long 0x00008000,0,0,0
ultimate_bit:
.long 0x00004000,0,0,0
top_mask:
.long 0xFFFF8000,0,0,0
one:
.long 0x3f800000,0,0,0
half:
.long 0x3f000000,0,0,0
one_point_five:
.long 0x3fc00000,0,0,0
magic1:
.long 0x60000000,0,0,0
magic2:
.long 0x3c000000,0,0,0
magic3:
.long 0x000047ff,0,0,0
_rsqrt_inaccurate:
rsqrt_inaccurate:
movd xmm0, edi
rsqrtss xmm0, xmm0
movd eax, xmm0
ret
_rsqrt_full:
rsqrt_full:
movd xmm0, edi
pand xmm0, [rip + top_mask]
por xmm0, [rip + penultimate_bit]
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad
sqrtss xmm0, xmm0
movd xmm1, [rip + one]
divss xmm1, xmm0
paddd xmm1, [rip + ultimate_bit]
pand xmm1, [rip + top_mask]
movd eax, xmm1
ret
_rsqrt_full_gpr:
rsqrt_full_gpr:
movd eax, xmm0 # Emulate regalloc mov
mov eax, edi
and eax, 0xFFFF8000
or eax, 0x00008000
movd xmm0, eax
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad
sqrtss xmm0, xmm0
movd xmm1, [rip + one]
divss xmm1, xmm0
movd eax, xmm1
add eax, 0x00004000
and eax, 0xffff8000
movd xmm0, eax # Emulate regalloc mov
ret
_rsqrt_full_nb2:
rsqrt_full_nb2:
movd xmm0, edi
pand xmm0, [rip + top_mask]
por xmm0, [rip + penultimate_bit]
ucomiss xmm0, [rip + min_pos_denorm]
jna rsqrt_full_bad_new1
sqrtss xmm0, xmm0
movd xmm1, [rip + one]
divss xmm1, xmm0
paddd xmm1, [rip + ultimate_bit]
pand xmm1, [rip + top_mask]
movd eax, xmm1
ret
_rsqrt_full_nb:
rsqrt_full_nb:
movd xmm0, edi
pand xmm0, [rip + top_mask]
por xmm0, [rip + penultimate_bit]
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad_new1
sqrtss xmm0, xmm0
movd xmm1, [rip + one]
divss xmm1, xmm0
paddd xmm1, [rip + ultimate_bit]
pand xmm1, [rip + top_mask]
movd eax, xmm1
ret
rsqrt_full_bad_new1:
cmp edi, 0x00800000
jb rsqrt_full_bad_new_fallback1
movd xmm0, edi
rsqrtss xmm1, xmm0
ucomiss xmm1, xmm1
jp rsqrt_full_bad_new1_nan
movd eax, xmm1
ret
rsqrt_full_bad_new_fallback1:
call _rsqrt_fallback
ret
rsqrt_full_bad_new1_nan:
ucomiss xmm0, xmm0
jp rsqrt_full_bad_new1_nan_ret
mov eax, 0x7FC00000
ret
rsqrt_full_bad_new1_nan_ret:
ret
_rsqrt_full_nb_gpr:
rsqrt_full_nb_gpr:
movd eax, xmm0 # Emulate regalloc mov
mov eax, edi
and eax, 0xFFFF8000
or eax, 0x00008000
movd xmm0, eax
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad_new2
sqrtss xmm0, xmm0
movd xmm1, [rip + one]
divss xmm1, xmm0
movd eax, xmm1
add eax, 0x00004000
and eax, 0xffff8000
movd xmm0, eax # Emulate regalloc mov
ret
rsqrt_full_bad_new2:
cmp edi, 0x00800000
jb rsqrt_full_bad_new_fallback2
movd xmm0, edi
rsqrtss xmm1, xmm0
test edi, edi
js rsqrt_full_bad_new2_nan
movd eax, xmm1
ret
rsqrt_full_bad_new_fallback2:
call _rsqrt_fallback
ret
rsqrt_full_bad_new2_nan:
mov eax, 0x7FC00000
ret
rsqrt_full_bad:
xorps xmm1, xmm1
movd xmm0, edi
ucomiss xmm0, xmm1
jp rsqrt_full_nan
je rsqrt_full_zero
jc rsqrt_full_neg
cmp edi, 0x7F800000
je rsqrt_full_inf
# TODO: Full Denormal Implementation
call _rsqrt_fallback
ret
rsqrt_full_neg:
mov eax, 0x7FC00000
ret
rsqrt_full_inf:
xor eax, eax
ret
rsqrt_full_nan:
mov eax, edi
or eax, 0x00400000
ret
rsqrt_full_zero:
mov eax, edi
or eax, 0x7F800000
ret
_rsqrt_newton:
rsqrt_newton:
movd xmm0, edi
pand xmm0, [rip + top_mask]
por xmm0, [rip + penultimate_bit]
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad
rsqrtps xmm1, xmm0
mulss xmm0, [rip + half]
vmulss xmm2, xmm1, xmm1
mulss xmm2, xmm0
movaps xmm0, [rip + one_point_five]
subss xmm0, xmm2
mulss xmm0, xmm1
paddd xmm0, [rip + ultimate_bit]
pand xmm0, [rip + top_mask]
movd eax, xmm0
ret
_rsqrt_hack:
rsqrt_hack:
movd xmm9, edi
vpand xmm0, xmm9, [rip + top_mask]
por xmm0, [rip + penultimate_bit]
# detect NaNs, negatives, zeros, denormals and infinities
vcmpngt_uqss xmm1, xmm0, [rip + min_pos_denorm]
ptest xmm1, xmm1
jnz rsqrt_full_bad
# calculate x64 estimate
rsqrtps xmm0, xmm0
# calculate correction factor
vpslld xmm1, xmm9, 8
vpsrad xmm2, xmm1, 31
paddd xmm1, [rip + magic1]
pcmpgtd xmm1, [rip + magic2]
pxor xmm1, xmm2
movaps xmm2, [rip + magic3]
psubd xmm2, xmm1
# correct x64 estimate
paddd xmm0, xmm2
pand xmm0, [rip + top_mask]
movd eax, xmm0
ret

147
externals/dynarmic/tests/unicorn_emu/a32_unicorn.cpp vendored
View File

@@ -3,25 +3,28 @@
* SPDX-License-Identifier: 0BSD
*/
#include <type_traits>
#include "A32/testenv.h"
#include "a32_unicorn.h"
#include "common/assert.h"
#include "common/bit_util.h"
#include "./a32_unicorn.h"
#define CHECKED(expr) \
do { \
if (auto cerr_ = (expr)) { \
ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \
uc_strerror(cerr_)); \
} \
#include <type_traits>
#include "../A32/testenv.h"
#include "dynarmic/common/assert.h"
#include "dynarmic/common/bit_util.h"
#define CHECKED(expr) \
do { \
if (auto cerr_ = (expr)) { \
ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \
uc_strerror(cerr_)); \
} \
} while (0)
constexpr u32 BEGIN_ADDRESS = 0;
constexpr u32 END_ADDRESS = ~u32(0);
template <class TestEnvironment>
A32Unicorn<TestEnvironment>::A32Unicorn(TestEnvironment& testenv) : testenv{testenv} {
template<class TestEnvironment>
A32Unicorn<TestEnvironment>::A32Unicorn(TestEnvironment& testenv)
: testenv{testenv} {
constexpr uc_mode open_mode = std::is_same_v<TestEnvironment, ArmTestEnv> ? UC_MODE_ARM : UC_MODE_THUMB;
CHECKED(uc_open(UC_ARCH_ARM, open_mode, &uc));
@@ -30,7 +33,7 @@ A32Unicorn<TestEnvironment>::A32Unicorn(TestEnvironment& testenv) : testenv{test
CHECKED(uc_hook_add(uc, &mem_write_prot_hook, UC_HOOK_MEM_WRITE, (void*)MemoryWriteHook, this, BEGIN_ADDRESS, END_ADDRESS));
}
template <class TestEnvironment>
template<class TestEnvironment>
A32Unicorn<TestEnvironment>::~A32Unicorn() {
ClearPageCache();
CHECKED(uc_hook_del(uc, intr_hook));
@@ -38,7 +41,7 @@ A32Unicorn<TestEnvironment>::~A32Unicorn() {
CHECKED(uc_close(uc));
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::Run() {
// Thumb execution mode requires the LSB to be set to 1.
constexpr u64 pc_mask = std::is_same_v<TestEnvironment, ArmTestEnv> ? 0 : 1;
@@ -61,36 +64,50 @@ void A32Unicorn<TestEnvironment>::Run() {
SetPC(new_pc);
}
template <class TestEnvironment>
template<class TestEnvironment>
u32 A32Unicorn<TestEnvironment>::GetPC() const {
u32 pc;
CHECKED(uc_reg_read(uc, UC_ARM_REG_PC, &pc));
return pc;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetPC(u32 value) {
CHECKED(uc_reg_write(uc, UC_ARM_REG_PC, &value));
}
template <class TestEnvironment>
template<class TestEnvironment>
u32 A32Unicorn<TestEnvironment>::GetSP() const {
u32 sp;
CHECKED(uc_reg_read(uc, UC_ARM_REG_SP, &sp));
return sp;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetSP(u32 value) {
CHECKED(uc_reg_write(uc, UC_ARM_REG_SP, &value));
}
constexpr std::array<int, Unicorn::A32::num_gprs> gpr_ids{
UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R2, UC_ARM_REG_R3, UC_ARM_REG_R4, UC_ARM_REG_R5, UC_ARM_REG_R6, UC_ARM_REG_R7,
UC_ARM_REG_R8, UC_ARM_REG_R9, UC_ARM_REG_R10, UC_ARM_REG_R11, UC_ARM_REG_R12, UC_ARM_REG_R13, UC_ARM_REG_R14, UC_ARM_REG_R15,
UC_ARM_REG_R0,
UC_ARM_REG_R1,
UC_ARM_REG_R2,
UC_ARM_REG_R3,
UC_ARM_REG_R4,
UC_ARM_REG_R5,
UC_ARM_REG_R6,
UC_ARM_REG_R7,
UC_ARM_REG_R8,
UC_ARM_REG_R9,
UC_ARM_REG_R10,
UC_ARM_REG_R11,
UC_ARM_REG_R12,
UC_ARM_REG_R13,
UC_ARM_REG_R14,
UC_ARM_REG_R15,
};
template <class TestEnvironment>
template<class TestEnvironment>
Unicorn::A32::RegisterArray A32Unicorn<TestEnvironment>::GetRegisters() const {
Unicorn::A32::RegisterArray regs{};
Unicorn::A32::RegisterPtrArray ptrs;
@@ -103,7 +120,7 @@ Unicorn::A32::RegisterArray A32Unicorn<TestEnvironment>::GetRegisters() const {
return regs;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetRegisters(const RegisterArray& value) {
Unicorn::A32::RegisterConstPtrArray ptrs;
for (size_t i = 0; i < ptrs.size(); ++i) {
@@ -114,22 +131,50 @@ void A32Unicorn<TestEnvironment>::SetRegisters(const RegisterArray& value) {
reinterpret_cast<void**>(const_cast<u32**>(ptrs.data())), static_cast<int>(ptrs.size())));
}
using DoubleExtRegPtrArray = std::array<Unicorn::A32::ExtRegArray::pointer, Unicorn::A32::num_ext_regs/2>;
using DoubleExtRegConstPtrArray = std::array<Unicorn::A32::ExtRegArray::const_pointer, Unicorn::A32::num_ext_regs/2>;
using DoubleExtRegPtrArray = std::array<Unicorn::A32::ExtRegArray::pointer, Unicorn::A32::num_ext_regs / 2>;
using DoubleExtRegConstPtrArray = std::array<Unicorn::A32::ExtRegArray::const_pointer, Unicorn::A32::num_ext_regs / 2>;
constexpr std::array<int, Unicorn::A32::num_ext_regs/2> double_ext_reg_ids{
UC_ARM_REG_D0, UC_ARM_REG_D1, UC_ARM_REG_D2, UC_ARM_REG_D3, UC_ARM_REG_D4, UC_ARM_REG_D5, UC_ARM_REG_D6, UC_ARM_REG_D7,
UC_ARM_REG_D8, UC_ARM_REG_D9, UC_ARM_REG_D10, UC_ARM_REG_D11, UC_ARM_REG_D12, UC_ARM_REG_D13, UC_ARM_REG_D14, UC_ARM_REG_D15,
UC_ARM_REG_D16, UC_ARM_REG_D17, UC_ARM_REG_D18, UC_ARM_REG_D19, UC_ARM_REG_D20, UC_ARM_REG_D21, UC_ARM_REG_D22, UC_ARM_REG_D23,
UC_ARM_REG_D24, UC_ARM_REG_D25, UC_ARM_REG_D26, UC_ARM_REG_D27, UC_ARM_REG_D28, UC_ARM_REG_D29, UC_ARM_REG_D30, UC_ARM_REG_D31,
constexpr std::array<int, Unicorn::A32::num_ext_regs / 2> double_ext_reg_ids{
UC_ARM_REG_D0,
UC_ARM_REG_D1,
UC_ARM_REG_D2,
UC_ARM_REG_D3,
UC_ARM_REG_D4,
UC_ARM_REG_D5,
UC_ARM_REG_D6,
UC_ARM_REG_D7,
UC_ARM_REG_D8,
UC_ARM_REG_D9,
UC_ARM_REG_D10,
UC_ARM_REG_D11,
UC_ARM_REG_D12,
UC_ARM_REG_D13,
UC_ARM_REG_D14,
UC_ARM_REG_D15,
UC_ARM_REG_D16,
UC_ARM_REG_D17,
UC_ARM_REG_D18,
UC_ARM_REG_D19,
UC_ARM_REG_D20,
UC_ARM_REG_D21,
UC_ARM_REG_D22,
UC_ARM_REG_D23,
UC_ARM_REG_D24,
UC_ARM_REG_D25,
UC_ARM_REG_D26,
UC_ARM_REG_D27,
UC_ARM_REG_D28,
UC_ARM_REG_D29,
UC_ARM_REG_D30,
UC_ARM_REG_D31,
};
template <class TestEnvironment>
template<class TestEnvironment>
Unicorn::A32::ExtRegArray A32Unicorn<TestEnvironment>::GetExtRegs() const {
Unicorn::A32::ExtRegArray ext_regs{};
DoubleExtRegPtrArray ptrs;
for (size_t i = 0; i < ptrs.size(); ++i)
ptrs[i] = &ext_regs[i*2];
ptrs[i] = &ext_regs[i * 2];
CHECKED(uc_reg_read_batch(uc, const_cast<int*>(double_ext_reg_ids.data()),
reinterpret_cast<void**>(ptrs.data()), static_cast<int>(ptrs.size())));
@@ -137,60 +182,60 @@ Unicorn::A32::ExtRegArray A32Unicorn<TestEnvironment>::GetExtRegs() const {
return ext_regs;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetExtRegs(const ExtRegArray& value) {
DoubleExtRegConstPtrArray ptrs;
for (size_t i = 0; i < ptrs.size(); ++i) {
ptrs[i] = &value[i*2];
ptrs[i] = &value[i * 2];
}
CHECKED(uc_reg_write_batch(uc, const_cast<int*>(double_ext_reg_ids.data()),
reinterpret_cast<void* const *>(const_cast<u32**>(ptrs.data())), static_cast<int>(ptrs.size())));
reinterpret_cast<void* const*>(const_cast<u32**>(ptrs.data())), static_cast<int>(ptrs.size())));
}
template <class TestEnvironment>
template<class TestEnvironment>
u32 A32Unicorn<TestEnvironment>::GetFpscr() const {
u32 fpsr;
CHECKED(uc_reg_read(uc, UC_ARM_REG_FPSCR, &fpsr));
return fpsr;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetFpscr(u32 value) {
CHECKED(uc_reg_write(uc, UC_ARM_REG_FPSCR, &value));
}
template <class TestEnvironment>
template<class TestEnvironment>
u32 A32Unicorn<TestEnvironment>::GetFpexc() const {
u32 value = 0;
CHECKED(uc_reg_read(uc, UC_ARM_REG_FPEXC, &value));
return value;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetFpexc(u32 value) {
CHECKED(uc_reg_write(uc, UC_ARM_REG_FPEXC, &value));
}
template <class TestEnvironment>
template<class TestEnvironment>
u32 A32Unicorn<TestEnvironment>::GetCpsr() const {
u32 pstate;
CHECKED(uc_reg_read(uc, UC_ARM_REG_CPSR, &pstate));
return pstate;
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::SetCpsr(u32 value) {
CHECKED(uc_reg_write(uc, UC_ARM_REG_CPSR, &value));
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::EnableFloatingPointAccess() {
const u32 new_fpexc = GetFpexc() | (1U << 30);
SetFpexc(new_fpexc);
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::ClearPageCache() {
for (const auto& page : pages) {
CHECKED(uc_mem_unmap(uc, page->address, 4096));
@@ -198,7 +243,7 @@ void A32Unicorn<TestEnvironment>::ClearPageCache() {
pages.clear();
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::DumpMemoryInformation() {
uc_mem_region* regions;
u32 count;
@@ -211,7 +256,7 @@ void A32Unicorn<TestEnvironment>::DumpMemoryInformation() {
CHECKED(uc_free(regions));
}
template <class TestEnvironment>
template<class TestEnvironment>
void A32Unicorn<TestEnvironment>::InterruptHook(uc_engine* /*uc*/, u32 int_number, void* user_data) {
auto* this_ = static_cast<A32Unicorn*>(user_data);
@@ -222,7 +267,7 @@ void A32Unicorn<TestEnvironment>::InterruptHook(uc_engine* /*uc*/, u32 int_numbe
auto iss = esr & 0xFFFFFF;
switch (ec) {
case 0x15: // SVC
case 0x15: // SVC
this_->testenv.CallSVC(iss);
break;
default:
@@ -231,7 +276,7 @@ void A32Unicorn<TestEnvironment>::InterruptHook(uc_engine* /*uc*/, u32 int_numbe
}
}
template <class TestEnvironment>
template<class TestEnvironment>
bool A32Unicorn<TestEnvironment>::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u32 start_address, int size, u64 /*value*/, void* user_data) {
auto* this_ = static_cast<A32Unicorn*>(user_data);
@@ -252,7 +297,7 @@ bool A32Unicorn<TestEnvironment>::UnmappedMemoryHook(uc_engine* uc, uc_mem_type
uc_err err = uc_mem_map_ptr(uc, base_address, page->data.size(), permissions, page->data.data());
if (err == UC_ERR_MAP)
return; // page already exists
return; // page already exists
CHECKED(err);
this_->pages.emplace_back(std::move(page));
@@ -260,8 +305,8 @@ bool A32Unicorn<TestEnvironment>::UnmappedMemoryHook(uc_engine* uc, uc_mem_type
const auto is_in_range = [](u32 addr, u32 start, u32 end) {
if (start <= end)
return addr >= start && addr <= end; // fffff[tttttt]fffff
return addr >= start || addr <= end; // ttttt]ffffff[ttttt
return addr >= start && addr <= end; // fffff[tttttt]fffff
return addr >= start || addr <= end; // ttttt]ffffff[ttttt
};
const u32 start_address_page = start_address & ~u32(0xFFF);
@@ -276,7 +321,7 @@ bool A32Unicorn<TestEnvironment>::UnmappedMemoryHook(uc_engine* uc, uc_mem_type
return true;
}
template <class TestEnvironment>
template<class TestEnvironment>
bool A32Unicorn<TestEnvironment>::MemoryWriteHook(uc_engine* /*uc*/, uc_mem_type /*type*/, u32 start_address, int size, u64 value, void* user_data) {
auto* this_ = static_cast<A32Unicorn*>(user_data);

17
externals/dynarmic/tests/unicorn_emu/a32_unicorn.h vendored
View File

@@ -9,16 +9,15 @@
#include <vector>
#ifdef _MSC_VER
#pragma warning(push, 0)
#include <unicorn/unicorn.h>
#pragma warning(pop)
# pragma warning(push, 0)
# include <unicorn/unicorn.h>
# pragma warning(pop)
#else
#include <unicorn/unicorn.h>
# include <unicorn/unicorn.h>
#endif
#include "common/common_types.h"
#include "A32/testenv.h"
#include "../A32/testenv.h"
#include "dynarmic/common/common_types.h"
namespace Unicorn::A32 {
static constexpr size_t num_gprs = 16;
@@ -28,9 +27,9 @@ using ExtRegArray = std::array<u32, num_ext_regs>;
using RegisterArray = std::array<u32, num_gprs>;
using RegisterPtrArray = std::array<RegisterArray::pointer, num_gprs>;
using RegisterConstPtrArray = std::array<RegisterArray::const_pointer, num_gprs>;
} // namespace Unicorn::A32
} // namespace Unicorn::A32
template <class TestEnvironment>
template<class TestEnvironment>
class A32Unicorn final {
public:
using ExtRegArray = Unicorn::A32::ExtRegArray;

36
externals/dynarmic/tests/unicorn_emu/a64_unicorn.cpp vendored
View File

@@ -3,21 +3,23 @@
* SPDX-License-Identifier: 0BSD
*/
#include "common/assert.h"
#include "a64_unicorn.h"
#include "./a64_unicorn.h"
#define CHECKED(expr) \
do { \
if (auto cerr_ = (expr)) { \
ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \
uc_strerror(cerr_)); \
} \
#include "dynarmic/common/assert.h"
#define CHECKED(expr) \
do { \
if (auto cerr_ = (expr)) { \
ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", cerr_, \
uc_strerror(cerr_)); \
} \
} while (0)
constexpr u64 BEGIN_ADDRESS = 0;
constexpr u64 END_ADDRESS = ~u64(0);
A64Unicorn::A64Unicorn(A64TestEnv& testenv) : testenv(testenv) {
A64Unicorn::A64Unicorn(A64TestEnv& testenv)
: testenv(testenv) {
CHECKED(uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc));
u64 fpv = 3 << 20;
CHECKED(uc_reg_write(uc, UC_ARM64_REG_CPACR_EL1, &fpv));
@@ -66,8 +68,7 @@ constexpr std::array<int, A64Unicorn::num_gprs> gpr_ids{
UC_ARM64_REG_X0, UC_ARM64_REG_X1, UC_ARM64_REG_X2, UC_ARM64_REG_X3, UC_ARM64_REG_X4, UC_ARM64_REG_X5, UC_ARM64_REG_X6, UC_ARM64_REG_X7,
UC_ARM64_REG_X8, UC_ARM64_REG_X9, UC_ARM64_REG_X10, UC_ARM64_REG_X11, UC_ARM64_REG_X12, UC_ARM64_REG_X13, UC_ARM64_REG_X14, UC_ARM64_REG_X15,
UC_ARM64_REG_X16, UC_ARM64_REG_X17, UC_ARM64_REG_X18, UC_ARM64_REG_X19, UC_ARM64_REG_X20, UC_ARM64_REG_X21, UC_ARM64_REG_X22, UC_ARM64_REG_X23,
UC_ARM64_REG_X24, UC_ARM64_REG_X25, UC_ARM64_REG_X26, UC_ARM64_REG_X27, UC_ARM64_REG_X28, UC_ARM64_REG_X29, UC_ARM64_REG_X30
};
UC_ARM64_REG_X24, UC_ARM64_REG_X25, UC_ARM64_REG_X26, UC_ARM64_REG_X27, UC_ARM64_REG_X28, UC_ARM64_REG_X29, UC_ARM64_REG_X30};
A64Unicorn::RegisterArray A64Unicorn::GetRegisters() const {
RegisterArray regs{};
@@ -93,8 +94,7 @@ constexpr std::array<int, A64Unicorn::num_vecs> vec_ids{
UC_ARM64_REG_Q0, UC_ARM64_REG_Q1, UC_ARM64_REG_Q2, UC_ARM64_REG_Q3, UC_ARM64_REG_Q4, UC_ARM64_REG_Q5, UC_ARM64_REG_Q6, UC_ARM64_REG_Q7,
UC_ARM64_REG_Q8, UC_ARM64_REG_Q9, UC_ARM64_REG_Q10, UC_ARM64_REG_Q11, UC_ARM64_REG_Q12, UC_ARM64_REG_Q13, UC_ARM64_REG_Q14, UC_ARM64_REG_Q15,
UC_ARM64_REG_Q16, UC_ARM64_REG_Q17, UC_ARM64_REG_Q18, UC_ARM64_REG_Q19, UC_ARM64_REG_Q20, UC_ARM64_REG_Q21, UC_ARM64_REG_Q22, UC_ARM64_REG_Q23,
UC_ARM64_REG_Q24, UC_ARM64_REG_Q25, UC_ARM64_REG_Q26, UC_ARM64_REG_Q27, UC_ARM64_REG_Q28, UC_ARM64_REG_Q29, UC_ARM64_REG_Q30, UC_ARM64_REG_Q31
};
UC_ARM64_REG_Q24, UC_ARM64_REG_Q25, UC_ARM64_REG_Q26, UC_ARM64_REG_Q27, UC_ARM64_REG_Q28, UC_ARM64_REG_Q29, UC_ARM64_REG_Q30, UC_ARM64_REG_Q31};
A64Unicorn::VectorArray A64Unicorn::GetVectors() const {
VectorArray vecs{};
@@ -114,7 +114,7 @@ void A64Unicorn::SetVectors(const VectorArray& value) {
ptrs[i] = &value[i];
CHECKED(uc_reg_write_batch(uc, const_cast<int*>(vec_ids.data()),
reinterpret_cast<void* const *>(const_cast<Vector**>(ptrs.data())), static_cast<int>(num_vecs)));
reinterpret_cast<void* const*>(const_cast<Vector**>(ptrs.data())), static_cast<int>(num_vecs)));
}
u32 A64Unicorn::GetFpcr() const {
@@ -176,7 +176,7 @@ void A64Unicorn::InterruptHook(uc_engine* uc, u32 int_number, void* user_data) {
auto iss = esr & 0xFFFFFF;
switch (ec) {
case 0x15: // SVC
case 0x15: // SVC
this_->testenv.CallSVC(iss);
break;
default:
@@ -204,7 +204,7 @@ bool A64Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u64 sta
uc_err err = uc_mem_map_ptr(uc, base_address, page->data.size(), permissions, page->data.data());
if (err == UC_ERR_MAP)
return; // page already exists
return; // page already exists
CHECKED(err);
this_->pages.emplace_back(std::move(page));
@@ -212,8 +212,8 @@ bool A64Unicorn::UnmappedMemoryHook(uc_engine* uc, uc_mem_type /*type*/, u64 sta
const auto is_in_range = [](u64 addr, u64 start, u64 end) {
if (start <= end)
return addr >= start && addr <= end; // fffff[tttttt]fffff
return addr >= start || addr <= end; // ttttt]ffffff[ttttt
return addr >= start && addr <= end; // fffff[tttttt]fffff
return addr >= start || addr <= end; // ttttt]ffffff[ttttt
};
const u64 start_address_page = start_address & ~u64(0xFFF);

12
externals/dynarmic/tests/unicorn_emu/a64_unicorn.h vendored
View File

@@ -9,15 +9,15 @@
#include <vector>
#ifdef _MSC_VER
#pragma warning(push, 0)
#include <unicorn/unicorn.h>
#pragma warning(pop)
# pragma warning(push, 0)
# include <unicorn/unicorn.h>
# pragma warning(pop)
#else
#include <unicorn/unicorn.h>
# include <unicorn/unicorn.h>
#endif
#include "common/common_types.h"
#include "A64/testenv.h"
#include "../A64/testenv.h"
#include "dynarmic/common/common_types.h"
class A64Unicorn final {
public: