early-access version 1730
This commit is contained in:
pineappleEA
255
externals/dynarmic/tests/A32/fuzz_thumb.cpp
vendored
255
externals/dynarmic/tests/A32/fuzz_thumb.cpp
vendored
@@ -14,20 +14,19 @@
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#include <catch.hpp>
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#include <dynarmic/A32/a32.h>
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#include "common/bit_util.h"
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#include "common/common_types.h"
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#include "frontend/A32/disassembler/disassembler.h"
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#include "frontend/A32/FPSCR.h"
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#include "frontend/A32/location_descriptor.h"
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#include "frontend/A32/PSR.h"
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#include "frontend/A32/translate/translate.h"
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#include "frontend/ir/basic_block.h"
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#include "ir_opt/passes.h"
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#include "rand_int.h"
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#include "testenv.h"
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#include "unicorn_emu/a32_unicorn.h"
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#include "../rand_int.h"
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#include "../unicorn_emu/a32_unicorn.h"
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#include "./testenv.h"
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#include "dynarmic/common/bit_util.h"
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#include "dynarmic/common/common_types.h"
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#include "dynarmic/frontend/A32/FPSCR.h"
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#include "dynarmic/frontend/A32/PSR.h"
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#include "dynarmic/frontend/A32/disassembler/disassembler.h"
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#include "dynarmic/frontend/A32/location_descriptor.h"
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#include "dynarmic/frontend/A32/translate/translate.h"
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#include "dynarmic/interface/A32/a32.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/opt/passes.h"
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using namespace Dynarmic;
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@@ -42,7 +41,9 @@ using WriteRecords = std::map<u32, u8>;
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struct ThumbInstGen final {
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public:
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ThumbInstGen(std::string_view format, std::function<bool(u32)> is_valid = [](u32){ return true; }) : is_valid(is_valid) {
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ThumbInstGen(
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std::string_view format, std::function<bool(u32)> is_valid = [](u32) { return true; })
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: is_valid(is_valid) {
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REQUIRE((format.size() == 16 || format.size() == 32));
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const auto bit_size = format.size();
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@@ -96,18 +97,14 @@ private:
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std::function<bool(u32)> is_valid;
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};
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static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit,
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const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
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static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit, const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
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const auto interp_regs = uni.GetRegisters();
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const auto jit_regs = jit.Regs();
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return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) &&
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uni.GetCpsr() == jit.Cpsr() &&
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interp_write_records == jit_write_records;
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return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) && uni.GetCpsr() == jit.Cpsr() && interp_write_records == jit_write_records;
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}
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static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs,
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size_t instruction_count, size_t instructions_to_execute_count) {
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static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs, size_t instruction_count, size_t instructions_to_execute_count) {
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uni.ClearPageCache();
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jit.ClearCache();
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@@ -178,7 +175,7 @@ static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<Th
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size_t num_insts = 0;
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while (num_insts < instructions_to_execute_count) {
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A32::LocationDescriptor descriptor = {u32(num_insts * 4), cpsr, A32::FPSCR{}};
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IR::Block ir_block = A32::Translate(descriptor, [&test_env](u32 vaddr) { return test_env.MemoryReadCode(vaddr); }, {});
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IR::Block ir_block = A32::Translate(descriptor, &test_env, {});
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Optimization::A32GetSetElimination(ir_block);
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Optimization::DeadCodeElimination(ir_block);
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Optimization::A32ConstantMemoryReads(ir_block, &test_env);
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@@ -202,7 +199,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to
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// Prepare memory.
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test_env.code_mem.resize(instruction_count + 1);
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test_env.code_mem.back() = 0xE7FE; // b +#0
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test_env.code_mem.back() = 0xE7FE; // b +#0
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// Prepare test subjects
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A32Unicorn uni{test_env};
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@@ -210,7 +207,7 @@ void FuzzJitThumb16(const size_t instruction_count, const size_t instructions_to
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for (size_t run_number = 0; run_number < run_count; run_number++) {
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ThumbTestEnv::RegisterArray initial_regs;
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
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initial_regs[15] = 0;
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std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator);
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@@ -225,7 +222,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
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// Prepare memory.
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// A Thumb-32 instruction is 32-bits so we multiply our count
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test_env.code_mem.resize(instruction_count * 2 + 1);
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test_env.code_mem.back() = 0xE7FE; // b +#0
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test_env.code_mem.back() = 0xE7FE; // b +#0
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// Prepare test subjects
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A32Unicorn uni{test_env};
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@@ -233,7 +230,7 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
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for (size_t run_number = 0; run_number < run_count; run_number++) {
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ThumbTestEnv::RegisterArray initial_regs;
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
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std::generate_n(initial_regs.begin(), initial_regs.size() - 1, [] { return RandInt<u32>(0, 0xFFFFFFFF); });
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initial_regs[15] = 0;
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for (size_t i = 0; i < instruction_count; i++) {
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@@ -251,44 +248,44 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to
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TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
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const std::array instructions = {
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ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
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ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
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ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
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ThumbInstGen("010000ooooxxxxxx"), // Data Processing
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ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
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ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
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[](u32 inst){ return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
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[](u32 inst){ return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
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ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
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ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
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ThumbInstGen("1011101000xxxxxx"), // REV
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ThumbInstGen("1011101001xxxxxx"), // REV16
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ThumbInstGen("1011101011xxxxxx"), // REVSH
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ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
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ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
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ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
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ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
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ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
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ThumbInstGen("1011010xxxxxxxxx", // PUSH
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[](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
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[](u32 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
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ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
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ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
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ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
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ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
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ThumbInstGen("010000ooooxxxxxx"), // Data Processing
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ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
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ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
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[](u32 inst) { return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
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[](u32 inst) { return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
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ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
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ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
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ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
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ThumbInstGen("1011101000xxxxxx"), // REV
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ThumbInstGen("1011101001xxxxxx"), // REV16
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ThumbInstGen("1011101011xxxxxx"), // REVSH
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ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
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ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
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ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
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ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
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ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
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ThumbInstGen("1011010xxxxxxxxx", // PUSH
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[](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
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[](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
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ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
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[](u32 inst) {
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// Ensure that the architecturally undefined case of
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// the base register being within the list isn't hit.
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const u32 rn = Common::Bits<8, 10>(inst);
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return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0;
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}),
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// TODO: We should properly test against swapped
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// endianness cases, however Unicorn doesn't
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// expose the intended endianness of a load/store
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// operation to memory through its hooks.
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// TODO: We should properly test against swapped
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// endianness cases, however Unicorn doesn't
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// expose the intended endianness of a load/store
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// operation to memory through its hooks.
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#if 0
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ThumbInstGen("101101100101x000"), // SETEND
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#endif
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@@ -319,11 +316,11 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") {
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TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16]") {
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const std::array instructions = {
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// TODO: We currently can't test BX/BLX as we have
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// no way of preventing the unpredictable
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// condition from occurring with the current interface.
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// (bits zero and one within the specified register
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// must not be address<1:0> == '10'.
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// TODO: We currently can't test BX/BLX as we have
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// no way of preventing the unpredictable
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// condition from occurring with the current interface.
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// (bits zero and one within the specified register
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// must not be address<1:0> == '10'.
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#if 0
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ThumbInstGen("01000111xmmmm000", // BLX/BX
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[](u32 inst){
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@@ -331,21 +328,21 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
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return Rm != 15;
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}),
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#endif
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ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
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ThumbInstGen("11100xxxxxxxxxxx"), // B
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ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
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ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
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ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
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[](u32 inst){
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ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
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ThumbInstGen("11100xxxxxxxxxxx"), // B
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ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
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ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
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ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
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[](u32 inst) {
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const u32 c = Common::Bits<9, 12>(inst);
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return c < 0b1110; // Don't want SWI or undefined instructions.
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return c < 0b1110; // Don't want SWI or undefined instructions.
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}),
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ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
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ThumbInstGen("10110110011x0xxx"), // CPS
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ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
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ThumbInstGen("10110110011x0xxx"), // CPS
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// TODO: We currently have no control over the generated
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// values when creating new pages, so we can't
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// reliably test this yet.
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// TODO: We currently have no control over the generated
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// values when creating new pages, so we can't
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// reliably test this yet.
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#if 0
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ThumbInstGen("10111101xxxxxxxx"), // POP (R = 1)
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#endif
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@@ -369,122 +366,122 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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};
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const std::array instructions = {
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ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
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ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
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ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8
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ThumbInstGen("111110101000nnnn1111dddd0001mmmm", // QADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
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ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
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ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
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ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX
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ThumbInstGen("111110101110nnnn1111dddd0001mmmm", // QSAX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
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ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
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three_reg_not_r15),
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ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8
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ThumbInstGen("111110101100nnnn1111dddd0001mmmm", // QSUB8
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three_reg_not_r15),
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ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16
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ThumbInstGen("111110101101nnnn1111dddd0001mmmm", // QSUB16
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
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ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
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ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
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ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
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ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH
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[](u32 inst) {
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const auto d = Common::Bits<8, 11>(inst);
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const auto m = Common::Bits<0, 3>(inst);
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const auto n = Common::Bits<16, 19>(inst);
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return m == n && d != 15 && m != 15;
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}),
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ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
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ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
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ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX
|
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ThumbInstGen("111110101010nnnn1111dddd0000mmmm", // SASX
|
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three_reg_not_r15),
|
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ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
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ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
|
||||
three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
|
||||
ThumbInstGen("111110101000nnnn1111dddd0010mmmm", // SHADD8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
|
||||
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
|
||||
ThumbInstGen("111110101010nnnn1111dddd0010mmmm", // SHASX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
|
||||
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8
|
||||
ThumbInstGen("111110101100nnnn1111dddd0010mmmm", // SHSUB8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
|
||||
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
|
||||
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
|
||||
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
|
||||
ThumbInstGen("111110101101nnnn1111dddd0000mmmm", // SSUB16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8
|
||||
ThumbInstGen("111110101000nnnn1111dddd0100mmmm", // UADD8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
|
||||
ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
|
||||
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
|
||||
ThumbInstGen("111110101000nnnn1111dddd0110mmmm", // UHADD8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
|
||||
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
|
||||
ThumbInstGen("111110101010nnnn1111dddd0110mmmm", // UHASX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
|
||||
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8
|
||||
ThumbInstGen("111110101100nnnn1111dddd0110mmmm", // UHSUB8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
|
||||
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
|
||||
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
|
||||
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
|
||||
ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX
|
||||
ThumbInstGen("111110101110nnnn1111dddd0101mmmm", // UQSAX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8
|
||||
ThumbInstGen("111110101100nnnn1111dddd0101mmmm", // UQSUB8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16
|
||||
ThumbInstGen("111110101101nnnn1111dddd0101mmmm", // UQSUB16
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
|
||||
ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
|
||||
ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
|
||||
three_reg_not_r15),
|
||||
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
|
||||
ThumbInstGen("111110101101nnnn1111dddd0100mmmm", // USUB16
|
||||
three_reg_not_r15),
|
||||
};
|
||||
|
||||
@@ -510,7 +507,7 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu
|
||||
A32Unicorn<ThumbTestEnv> uni{test_env};
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
|
||||
constexpr ThumbTestEnv::RegisterArray initial_regs {
|
||||
constexpr ThumbTestEnv::RegisterArray initial_regs{
|
||||
0xe90ecd70,
|
||||
0x3e3b73c3,
|
||||
0x571616f9,
|
||||
@@ -530,12 +527,12 @@ TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb][Thu
|
||||
};
|
||||
|
||||
test_env.code_mem = {
|
||||
0x40B8, // lsls r0, r7, #0
|
||||
0x01CA, // lsls r2, r1, #7
|
||||
0x83A1, // strh r1, [r4, #28]
|
||||
0x708A, // strb r2, [r1, #2]
|
||||
0xBCC4, // pop {r2, r6, r7}
|
||||
0xE7FE, // b +#0
|
||||
0x40B8, // lsls r0, r7, #0
|
||||
0x01CA, // lsls r2, r1, #7
|
||||
0x83A1, // strh r1, [r4, #28]
|
||||
0x708A, // strb r2, [r1, #2]
|
||||
0xBCC4, // pop {r2, r6, r7}
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
RunInstance(1, test_env, uni, jit, initial_regs, 5, 5);
|
||||
|
||||
Reference in New Issue
Block a user