early-access version 1873
This commit is contained in:
parent
9b2ef88b7d
commit
1ddc7f992d
@ -1,7 +1,7 @@
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yuzu emulator early access
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yuzu emulator early access
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=============
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=============
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This is the source code for early-access 1871.
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This is the source code for early-access 1873.
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## Legal Notice
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## Legal Notice
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@ -29,6 +29,49 @@ IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32
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}
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}
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}
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}
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IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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const IR::U32 zero{ir.Imm32(0)};
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const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
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const IR::U1 z_flag{ir.GetZFlag()};
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const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
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const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
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: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
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ir.ILessThan(operand_2, zero, true))};
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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case CompareOp::LessThan:
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return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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case CompareOp::Equal:
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return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
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case CompareOp::LessThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::GreaterThan: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
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ir.IGreaterThan(intermediate, zero, true))};
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const IR::U1 not_z{ir.LogicalNot(z_flag)};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
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}
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case CompareOp::NotEqual:
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return ir.LogicalOr(ir.INotEqual(intermediate, zero),
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ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
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case CompareOp::GreaterThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
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ir.IGreaterThanEqual(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::True:
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return ir.Imm1(true);
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default:
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
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IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
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BooleanOp bop) {
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BooleanOp bop) {
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switch (bop) {
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switch (bop) {
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@ -11,6 +11,10 @@ namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
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const IR::U32& operand_2, CompareOp compare_op, bool is_signed);
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[[nodiscard]] IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, CompareOp compare_op,
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bool is_signed);
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop);
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const IR::U1& predicate_2, BooleanOp bop);
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@ -9,49 +9,6 @@
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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namespace {
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namespace {
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IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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const IR::U32 zero{ir.Imm32(0)};
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const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
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const IR::U1 z_flag{ir.GetZFlag()};
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const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
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const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
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: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
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ir.ILessThan(operand_2, zero, true))};
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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case CompareOp::LessThan:
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return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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case CompareOp::Equal:
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return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
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case CompareOp::LessThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::GreaterThan: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
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ir.IGreaterThan(intermediate, zero, true))};
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const IR::U1 not_z{ir.LogicalNot(z_flag)};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
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}
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case CompareOp::NotEqual:
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return ir.LogicalOr(ir.INotEqual(intermediate, zero),
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ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
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case CompareOp::GreaterThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
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ir.IGreaterThanEqual(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::True:
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return ir.Imm1(true);
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default:
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed, bool x) {
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CompareOp compare_op, bool is_signed, bool x) {
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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namespace Shader::Maxwell {
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namespace Shader::Maxwell {
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namespace {
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namespace {
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IR::U1 IsetpCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed, bool x) {
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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: IntegerCompare(ir, operand_1, operand_2, compare_op, is_signed);
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}
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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union {
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union {
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u64 raw;
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u64 raw;
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@ -17,15 +23,18 @@ void ISETP(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<8, 8, IR::Reg> src_reg_a;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<43, 1, u64> x;
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BitField<45, 2, BooleanOp> bop;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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BitField<49, 3, CompareOp> compare_op;
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BitField<49, 3, CompareOp> compare_op;
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} const isetp{insn};
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} const isetp{insn};
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const bool is_signed{isetp.is_signed != 0};
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const bool x{isetp.x != 0};
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const BooleanOp bop{isetp.bop};
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const BooleanOp bop{isetp.bop};
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const CompareOp compare_op{isetp.compare_op};
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const CompareOp compare_op{isetp.compare_op};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U32 op_a{v.X(isetp.src_reg_a)};
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const IR::U1 comparison{IntegerCompare(v.ir, op_a, op_b, compare_op, isetp.is_signed != 0)};
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const IR::U1 comparison{IsetpCompare(v.ir, op_a, op_b, compare_op, is_signed, x)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 bop_pred{v.ir.GetPred(isetp.bop_pred, isetp.neg_bop_pred != 0)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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/// Pop asynchronous downloads
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/// Pop asynchronous downloads
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void PopAsyncFlushes();
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void PopAsyncFlushes();
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[[nodiscard]] bool DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount);
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bool DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount);
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bool DMAClear(GPUVAddr src_address, u64 amount, u32 value);
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/// Return true when a CPU region is modified from the GPU
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/// Return true when a CPU region is modified from the GPU
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[[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size);
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[[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size);
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/// Return true when a region is registered on the cache
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[[nodiscard]] bool IsRegionRegistered(VAddr addr, size_t size);
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/// Return true when a CPU region is modified from the CPU
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/// Return true when a CPU region is modified from the CPU
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[[nodiscard]] bool IsRegionCpuModified(VAddr addr, size_t size);
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[[nodiscard]] bool IsRegionCpuModified(VAddr addr, size_t size);
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@ -516,8 +521,8 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
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if (!cpu_src_address || !cpu_dest_address) {
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if (!cpu_src_address || !cpu_dest_address) {
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return false;
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return false;
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}
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}
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const bool source_dirty = IsRegionGpuModified(*cpu_src_address, amount);
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const bool source_dirty = IsRegionRegistered(*cpu_src_address, amount);
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const bool dest_dirty = IsRegionGpuModified(*cpu_dest_address, amount);
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const bool dest_dirty = IsRegionRegistered(*cpu_dest_address, amount);
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if (!source_dirty && !dest_dirty) {
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if (!source_dirty && !dest_dirty) {
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return false;
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return false;
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}
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}
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@ -562,7 +567,7 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
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}
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}
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runtime.CopyBuffer(dest_buffer, src_buffer, copies);
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runtime.CopyBuffer(dest_buffer, src_buffer, copies);
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if (source_dirty) {
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if (IsRegionGpuModified(*cpu_src_address, amount)) {
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dest_buffer.MarkRegionAsGpuModified(*cpu_dest_address, amount);
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dest_buffer.MarkRegionAsGpuModified(*cpu_dest_address, amount);
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}
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}
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std::vector<u8> tmp_buffer(amount);
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std::vector<u8> tmp_buffer(amount);
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@ -571,6 +576,37 @@ bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 am
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return true;
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return true;
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}
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}
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template <class P>
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bool BufferCache<P>::DMAClear(GPUVAddr dst_address, u64 amount, u32 value) {
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const std::optional<VAddr> cpu_dst_address = gpu_memory.GpuToCpuAddress(dst_address);
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if (!cpu_dst_address) {
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return false;
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}
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const bool dest_dirty = IsRegionRegistered(*cpu_dst_address, amount);
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if (!dest_dirty) {
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return false;
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}
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const IntervalType subtract_interval{*cpu_dst_address, *cpu_dst_address + amount * sizeof(u32)};
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uncommitted_ranges.subtract(subtract_interval);
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for (auto& interval_set : committed_ranges) {
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interval_set.subtract(subtract_interval);
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}
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common_ranges.subtract(subtract_interval);
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const size_t size = amount * sizeof(u32);
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BufferId buffer;
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do {
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has_deleted_buffers = false;
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buffer = FindBuffer(*cpu_dst_address, static_cast<u32>(size));
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} while (has_deleted_buffers);
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auto& dest_buffer = slot_buffers[buffer];
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const u32 offset = static_cast<u32>(*cpu_dst_address - dest_buffer.CpuAddr());
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runtime.ClearBuffer(dest_buffer, offset, size, value);
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return true;
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}
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template <class P>
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template <class P>
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void BufferCache<P>::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr,
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void BufferCache<P>::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr,
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u32 size) {
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u32 size) {
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@ -876,6 +912,27 @@ bool BufferCache<P>::IsRegionGpuModified(VAddr addr, size_t size) {
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return false;
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return false;
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}
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}
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template <class P>
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bool BufferCache<P>::IsRegionRegistered(VAddr addr, size_t size) {
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const VAddr end_addr = addr + size;
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const u64 page_end = Common::DivCeil(end_addr, PAGE_SIZE);
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for (u64 page = addr >> PAGE_BITS; page < page_end;) {
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const BufferId buffer_id = page_table[page];
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if (!buffer_id) {
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++page;
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continue;
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}
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Buffer& buffer = slot_buffers[buffer_id];
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const VAddr buf_start_addr = buffer.CpuAddr();
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const VAddr buf_end_addr = buf_start_addr + buffer.SizeBytes();
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if (buf_start_addr < end_addr && addr < buf_end_addr) {
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return true;
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}
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page = Common::DivCeil(end_addr, PAGE_SIZE);
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}
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return false;
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}
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template <class P>
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template <class P>
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bool BufferCache<P>::IsRegionCpuModified(VAddr addr, size_t size) {
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bool BufferCache<P>::IsRegionCpuModified(VAddr addr, size_t size) {
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const u64 page_end = Common::DivCeil(addr + size, PAGE_SIZE);
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const u64 page_end = Common::DivCeil(addr + size, PAGE_SIZE);
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@ -87,9 +87,11 @@ void MaxwellDMA::CopyPitchToPitch() {
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// TODO: allow multisized components.
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// TODO: allow multisized components.
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if (is_buffer_clear) {
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if (is_buffer_clear) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlock(regs.offset_out, reinterpret_cast<u8*>(tmp_buffer.data()),
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memory_manager.WriteBlockUnsafe(regs.offset_out,
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regs.line_length_in * sizeof(u32));
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reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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return;
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return;
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}
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}
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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@ -31,6 +31,8 @@ class AccelerateDMAInterface {
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public:
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public:
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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virtual bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) = 0;
|
virtual bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) = 0;
|
||||||
|
|
||||||
|
virtual bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) = 0;
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -145,6 +145,12 @@ void BufferCacheRuntime::CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void BufferCacheRuntime::ClearBuffer(Buffer& dest_buffer, u32 offset, size_t size, u32 value) {
|
||||||
|
glClearNamedBufferSubData(dest_buffer.Handle(), GL_R32UI, static_cast<GLintptr>(offset),
|
||||||
|
static_cast<GLsizeiptr>(size / sizeof(u32)), GL_RGBA, GL_UNSIGNED_INT,
|
||||||
|
&value);
|
||||||
|
}
|
||||||
|
|
||||||
void BufferCacheRuntime::BindIndexBuffer(Buffer& buffer, u32 offset, u32 size) {
|
void BufferCacheRuntime::BindIndexBuffer(Buffer& buffer, u32 offset, u32 size) {
|
||||||
if (has_unified_vertex_buffers) {
|
if (has_unified_vertex_buffers) {
|
||||||
buffer.MakeResident(GL_READ_ONLY);
|
buffer.MakeResident(GL_READ_ONLY);
|
||||||
|
@ -67,6 +67,8 @@ public:
|
|||||||
void CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer,
|
void CopyBuffer(Buffer& dst_buffer, Buffer& src_buffer,
|
||||||
std::span<const VideoCommon::BufferCopy> copies);
|
std::span<const VideoCommon::BufferCopy> copies);
|
||||||
|
|
||||||
|
void ClearBuffer(Buffer& dest_buffer, u32 offset, size_t size, u32 value);
|
||||||
|
|
||||||
void BindIndexBuffer(Buffer& buffer, u32 offset, u32 size);
|
void BindIndexBuffer(Buffer& buffer, u32 offset, u32 size);
|
||||||
|
|
||||||
void BindVertexBuffer(u32 index, Buffer& buffer, u32 offset, u32 size, u32 stride);
|
void BindVertexBuffer(u32 index, Buffer& buffer, u32 offset, u32 size, u32 stride);
|
||||||
|
@ -1051,4 +1051,9 @@ bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64
|
|||||||
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool AccelerateDMA::BufferClear(GPUVAddr src_address, u64 amount, u32 value) {
|
||||||
|
std::scoped_lock lock{buffer_cache.mutex};
|
||||||
|
return buffer_cache.DMAClear(src_address, amount, value);
|
||||||
|
}
|
||||||
|
|
||||||
} // namespace OpenGL
|
} // namespace OpenGL
|
||||||
|
@ -63,6 +63,8 @@ public:
|
|||||||
|
|
||||||
bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) override;
|
bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) override;
|
||||||
|
|
||||||
|
bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
BufferCache& buffer_cache;
|
BufferCache& buffer_cache;
|
||||||
};
|
};
|
||||||
|
@ -172,6 +172,30 @@ void BufferCacheRuntime::CopyBuffer(VkBuffer dst_buffer, VkBuffer src_buffer,
|
|||||||
});
|
});
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void BufferCacheRuntime::ClearBuffer(VkBuffer dest_buffer, u32 offset, size_t size, u32 value) {
|
||||||
|
static constexpr VkMemoryBarrier READ_BARRIER{
|
||||||
|
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
|
||||||
|
.pNext = nullptr,
|
||||||
|
.srcAccessMask = VK_ACCESS_MEMORY_WRITE_BIT,
|
||||||
|
.dstAccessMask = VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT,
|
||||||
|
};
|
||||||
|
static constexpr VkMemoryBarrier WRITE_BARRIER{
|
||||||
|
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
|
||||||
|
.pNext = nullptr,
|
||||||
|
.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
|
||||||
|
.dstAccessMask = VK_ACCESS_MEMORY_READ_BIT | VK_ACCESS_MEMORY_WRITE_BIT,
|
||||||
|
};
|
||||||
|
|
||||||
|
scheduler.RequestOutsideRenderPassOperationContext();
|
||||||
|
scheduler.Record([dest_buffer, offset, size, value](vk::CommandBuffer cmdbuf) {
|
||||||
|
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_ALL_COMMANDS_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT,
|
||||||
|
0, READ_BARRIER);
|
||||||
|
cmdbuf.FillBuffer(dest_buffer, offset, size, value);
|
||||||
|
cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
|
||||||
|
0, WRITE_BARRIER);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format,
|
void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format,
|
||||||
u32 base_vertex, u32 num_indices, VkBuffer buffer,
|
u32 base_vertex, u32 num_indices, VkBuffer buffer,
|
||||||
u32 offset, [[maybe_unused]] u32 size) {
|
u32 offset, [[maybe_unused]] u32 size) {
|
||||||
|
@ -72,6 +72,8 @@ public:
|
|||||||
void CopyBuffer(VkBuffer src_buffer, VkBuffer dst_buffer,
|
void CopyBuffer(VkBuffer src_buffer, VkBuffer dst_buffer,
|
||||||
std::span<const VideoCommon::BufferCopy> copies);
|
std::span<const VideoCommon::BufferCopy> copies);
|
||||||
|
|
||||||
|
void ClearBuffer(VkBuffer dest_buffer, u32 offset, size_t size, u32 value);
|
||||||
|
|
||||||
void BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, u32 num_indices,
|
void BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, u32 num_indices,
|
||||||
u32 base_vertex, VkBuffer buffer, u32 offset, u32 size);
|
u32 base_vertex, VkBuffer buffer, u32 offset, u32 size);
|
||||||
|
|
||||||
|
@ -541,6 +541,11 @@ void RasterizerVulkan::FlushWork() {
|
|||||||
|
|
||||||
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
|
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
|
||||||
|
|
||||||
|
bool AccelerateDMA::BufferClear(GPUVAddr src_address, u64 amount, u32 value) {
|
||||||
|
std::scoped_lock lock{buffer_cache.mutex};
|
||||||
|
return buffer_cache.DMAClear(src_address, amount, value);
|
||||||
|
}
|
||||||
|
|
||||||
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
|
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
|
||||||
std::scoped_lock lock{buffer_cache.mutex};
|
std::scoped_lock lock{buffer_cache.mutex};
|
||||||
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
||||||
|
@ -55,6 +55,8 @@ public:
|
|||||||
|
|
||||||
bool BufferCopy(GPUVAddr start_address, GPUVAddr end_address, u64 amount) override;
|
bool BufferCopy(GPUVAddr start_address, GPUVAddr end_address, u64 amount) override;
|
||||||
|
|
||||||
|
bool BufferClear(GPUVAddr src_address, u64 amount, u32 value) override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
BufferCache& buffer_cache;
|
BufferCache& buffer_cache;
|
||||||
};
|
};
|
||||||
|
Loading…
Reference in New Issue
Block a user