early-access version 3670
This commit is contained in:
parent
fbb35fcc7e
commit
27314341d7
@ -1,7 +1,7 @@
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yuzu emulator early access
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yuzu emulator early access
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=============
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=============
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This is the source code for early-access 3669.
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This is the source code for early-access 3670.
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## Legal Notice
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## Legal Notice
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3
externals/CMakeLists.txt
vendored
3
externals/CMakeLists.txt
vendored
@ -63,8 +63,9 @@ if (YUZU_USE_EXTERNAL_SDL2)
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# Yuzu itself needs: Atomic Audio Events Joystick Haptic Sensor Threads Timers
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# Yuzu itself needs: Atomic Audio Events Joystick Haptic Sensor Threads Timers
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# Since 2.0.18 Atomic+Threads required for HIDAPI/libusb (see https://github.com/libsdl-org/SDL/issues/5095)
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# Since 2.0.18 Atomic+Threads required for HIDAPI/libusb (see https://github.com/libsdl-org/SDL/issues/5095)
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# Yuzu-cmd also needs: Video (depends on Loadso/Dlopen)
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# Yuzu-cmd also needs: Video (depends on Loadso/Dlopen)
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# CPUinfo also required for SDL Audio, at least until 2.28.0 (see https://github.com/libsdl-org/SDL/issues/7809)
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set(SDL_UNUSED_SUBSYSTEMS
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set(SDL_UNUSED_SUBSYSTEMS
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CPUinfo File Filesystem
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File Filesystem
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Locale Power Render)
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Locale Power Render)
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foreach(_SUB ${SDL_UNUSED_SUBSYSTEMS})
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foreach(_SUB ${SDL_UNUSED_SUBSYSTEMS})
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string(TOUPPER ${_SUB} _OPT)
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string(TOUPPER ${_SUB} _OPT)
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@ -4,8 +4,6 @@
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add_library(core STATIC
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add_library(core STATIC
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arm/arm_interface.h
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arm/arm_interface.h
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arm/arm_interface.cpp
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arm/arm_interface.cpp
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arm/dynarmic/arm_exclusive_monitor.cpp
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arm/dynarmic/arm_exclusive_monitor.h
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arm/exclusive_monitor.cpp
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arm/exclusive_monitor.cpp
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arm/exclusive_monitor.h
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arm/exclusive_monitor.h
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arm/symbols.cpp
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arm/symbols.cpp
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@ -848,12 +846,15 @@ endif()
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if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64)
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if (ARCHITECTURE_x86_64 OR ARCHITECTURE_arm64)
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target_sources(core PRIVATE
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target_sources(core PRIVATE
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arm/dynarmic/arm_dynarmic.h
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arm/dynarmic/arm_dynarmic_64.cpp
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arm/dynarmic/arm_dynarmic_64.cpp
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arm/dynarmic/arm_dynarmic_64.h
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arm/dynarmic/arm_dynarmic_64.h
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arm/dynarmic/arm_dynarmic_32.cpp
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arm/dynarmic/arm_dynarmic_32.cpp
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arm/dynarmic/arm_dynarmic_32.h
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arm/dynarmic/arm_dynarmic_32.h
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arm/dynarmic/arm_dynarmic_cp15.cpp
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arm/dynarmic/dynarmic_cp15.cpp
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arm/dynarmic/arm_dynarmic_cp15.h
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arm/dynarmic/dynarmic_cp15.h
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arm/dynarmic/dynarmic_exclusive_monitor.cpp
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arm/dynarmic/dynarmic_exclusive_monitor.h
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hle/service/jit/jit_context.cpp
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hle/service/jit/jit_context.cpp
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hle/service/jit/jit_context.h
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hle/service/jit/jit_context.h
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hle/service/jit/jit.cpp
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hle/service/jit/jit.cpp
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@ -13,25 +13,68 @@
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#include "core/core.h"
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#include "core/core.h"
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#include "core/debugger/debugger.h"
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#include "core/debugger/debugger.h"
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#include "core/hle/kernel/k_process.h"
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#include "core/hle/kernel/k_process.h"
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#include "core/hle/kernel/k_thread.h"
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#include "core/hle/kernel/svc.h"
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#include "core/hle/kernel/svc.h"
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#include "core/loader/loader.h"
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#include "core/loader/loader.h"
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#include "core/memory.h"
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#include "core/memory.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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namespace Core {
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namespace Core {
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constexpr u64 SEGMENT_BASE = 0x7100000000ull;
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constexpr u64 SEGMENT_BASE = 0x7100000000ull;
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std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktraceFromContext(
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std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktraceFromContext(
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Core::System& system, const ARM_Interface::ThreadContext32& ctx) {
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Core::System& system, const ARM_Interface::ThreadContext32& ctx) {
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return ARM_Dynarmic_32::GetBacktraceFromContext(system, ctx);
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std::vector<BacktraceEntry> out;
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auto& memory = system.ApplicationMemory();
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const auto& reg = ctx.cpu_registers;
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u32 pc = reg[15], lr = reg[14], fp = reg[11];
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out.push_back({"", 0, pc, 0, ""});
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// fp (= r11) points to the last frame record.
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// Frame records are two words long:
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// fp+0 : pointer to previous frame record
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// fp+4 : value of lr for frame
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for (size_t i = 0; i < 256; i++) {
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out.push_back({"", 0, lr, 0, ""});
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if (!fp || (fp % 4 != 0) || !memory.IsValidVirtualAddressRange(fp, 8)) {
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break;
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}
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lr = memory.Read32(fp + 4);
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fp = memory.Read32(fp);
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}
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SymbolicateBacktrace(system, out);
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return out;
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}
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}
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std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktraceFromContext(
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std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktraceFromContext(
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Core::System& system, const ARM_Interface::ThreadContext64& ctx) {
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Core::System& system, const ARM_Interface::ThreadContext64& ctx) {
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return ARM_Dynarmic_64::GetBacktraceFromContext(system, ctx);
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std::vector<BacktraceEntry> out;
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auto& memory = system.ApplicationMemory();
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const auto& reg = ctx.cpu_registers;
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u64 pc = ctx.pc, lr = reg[30], fp = reg[29];
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out.push_back({"", 0, pc, 0, ""});
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// fp (= x29) points to the previous frame record.
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// Frame records are two words long:
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// fp+0 : pointer to previous frame record
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// fp+8 : value of lr for frame
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for (size_t i = 0; i < 256; i++) {
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out.push_back({"", 0, lr, 0, ""});
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if (!fp || (fp % 4 != 0) || !memory.IsValidVirtualAddressRange(fp, 16)) {
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break;
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}
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lr = memory.Read64(fp + 8);
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fp = memory.Read64(fp);
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}
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SymbolicateBacktrace(system, out);
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return out;
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}
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}
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void ARM_Interface::SymbolicateBacktrace(Core::System& system, std::vector<BacktraceEntry>& out) {
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void ARM_Interface::SymbolicateBacktrace(Core::System& system, std::vector<BacktraceEntry>& out) {
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@ -76,6 +119,18 @@ void ARM_Interface::SymbolicateBacktrace(Core::System& system, std::vector<Backt
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}
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}
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}
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}
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std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktrace() const {
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if (GetArchitecture() == Architecture::Aarch64) {
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ThreadContext64 ctx;
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SaveContext(ctx);
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return GetBacktraceFromContext(system, ctx);
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} else {
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ThreadContext32 ctx;
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SaveContext(ctx);
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return GetBacktraceFromContext(system, ctx);
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}
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}
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void ARM_Interface::LogBacktrace() const {
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void ARM_Interface::LogBacktrace() const {
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const VAddr sp = GetSP();
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const VAddr sp = GetSP();
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const VAddr pc = GetPC();
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const VAddr pc = GetPC();
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@ -83,7 +138,6 @@ void ARM_Interface::LogBacktrace() const {
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LOG_ERROR(Core_ARM, "{:20}{:20}{:20}{:20}{}", "Module Name", "Address", "Original Address",
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LOG_ERROR(Core_ARM, "{:20}{:20}{:20}{:20}{}", "Module Name", "Address", "Original Address",
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"Offset", "Symbol");
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"Offset", "Symbol");
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LOG_ERROR(Core_ARM, "");
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LOG_ERROR(Core_ARM, "");
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const auto backtrace = GetBacktrace();
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const auto backtrace = GetBacktrace();
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for (const auto& entry : backtrace) {
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for (const auto& entry : backtrace) {
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LOG_ERROR(Core_ARM, "{:20}{:016X} {:016X} {:016X} {}", entry.module, entry.address,
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LOG_ERROR(Core_ARM, "{:20}{:016X} {:016X} {:016X} {}", entry.module, entry.address,
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@ -97,7 +151,7 @@ void ARM_Interface::Run() {
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while (true) {
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while (true) {
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Kernel::KThread* current_thread{Kernel::GetCurrentThreadPointer(system.Kernel())};
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Kernel::KThread* current_thread{Kernel::GetCurrentThreadPointer(system.Kernel())};
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Dynarmic::HaltReason hr{};
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HaltReason hr{};
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// Notify the debugger and go to sleep if a step was performed
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// Notify the debugger and go to sleep if a step was performed
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// and this thread has been scheduled again.
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// and this thread has been scheduled again.
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@ -108,17 +162,17 @@ void ARM_Interface::Run() {
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}
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}
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// Otherwise, run the thread.
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// Otherwise, run the thread.
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system.EnterDynarmicProfile();
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system.EnterCPUProfile();
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if (current_thread->GetStepState() == StepState::StepPending) {
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if (current_thread->GetStepState() == StepState::StepPending) {
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hr = StepJit();
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hr = StepJit();
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if (Has(hr, step_thread)) {
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if (True(hr & HaltReason::StepThread)) {
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current_thread->SetStepState(StepState::StepPerformed);
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current_thread->SetStepState(StepState::StepPerformed);
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}
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}
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} else {
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} else {
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hr = RunJit();
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hr = RunJit();
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}
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}
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system.ExitDynarmicProfile();
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system.ExitCPUProfile();
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// If the thread is scheduled for termination, exit the thread.
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// If the thread is scheduled for termination, exit the thread.
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if (current_thread->HasDpc()) {
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if (current_thread->HasDpc()) {
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@ -130,8 +184,8 @@ void ARM_Interface::Run() {
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// Notify the debugger and go to sleep if a breakpoint was hit,
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// Notify the debugger and go to sleep if a breakpoint was hit,
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// or if the thread is unable to continue for any reason.
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// or if the thread is unable to continue for any reason.
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if (Has(hr, breakpoint) || Has(hr, no_execute)) {
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if (True(hr & HaltReason::InstructionBreakpoint) || True(hr & HaltReason::PrefetchAbort)) {
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if (!Has(hr, no_execute)) {
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if (!True(hr & HaltReason::InstructionBreakpoint)) {
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RewindBreakpointInstruction();
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RewindBreakpointInstruction();
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}
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}
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if (system.DebuggerEnabled()) {
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if (system.DebuggerEnabled()) {
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@ -144,7 +198,7 @@ void ARM_Interface::Run() {
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}
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}
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// Notify the debugger and go to sleep if a watchpoint was hit.
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// Notify the debugger and go to sleep if a watchpoint was hit.
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if (Has(hr, watchpoint)) {
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if (True(hr & HaltReason::DataAbort)) {
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if (system.DebuggerEnabled()) {
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if (system.DebuggerEnabled()) {
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system.GetDebugger().NotifyThreadWatchpoint(current_thread, *HaltedWatchpoint());
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system.GetDebugger().NotifyThreadWatchpoint(current_thread, *HaltedWatchpoint());
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}
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}
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@ -153,11 +207,11 @@ void ARM_Interface::Run() {
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}
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}
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// Handle syscalls and scheduling (this may change the current thread/core)
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// Handle syscalls and scheduling (this may change the current thread/core)
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if (Has(hr, svc_call)) {
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if (True(hr & HaltReason::SupervisorCall)) {
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Kernel::Svc::Call(system, GetSvcNumber());
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Kernel::Svc::Call(system, GetSvcNumber());
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break;
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break;
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}
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}
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if (Has(hr, break_loop) || !uses_wall_clock) {
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if (True(hr & HaltReason::BreakLoop) || !uses_wall_clock) {
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break;
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break;
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}
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}
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}
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}
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@ -8,8 +8,6 @@
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#include <string>
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#include <string>
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#include <vector>
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#include <vector>
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#include <dynarmic/interface/halt_reason.h>
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#include "common/common_funcs.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "core/hardware_properties.h"
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#include "core/hardware_properties.h"
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@ -30,6 +28,22 @@ class CPUInterruptHandler;
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using WatchpointArray = std::array<Kernel::DebugWatchpoint, Core::Hardware::NUM_WATCHPOINTS>;
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using WatchpointArray = std::array<Kernel::DebugWatchpoint, Core::Hardware::NUM_WATCHPOINTS>;
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// NOTE: these values match the HaltReason enum in Dynarmic
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enum class HaltReason : u64 {
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StepThread = 0x00000001,
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DataAbort = 0x00000004,
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BreakLoop = 0x02000000,
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SupervisorCall = 0x04000000,
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InstructionBreakpoint = 0x08000000,
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PrefetchAbort = 0x20000000,
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};
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DECLARE_ENUM_FLAG_OPERATORS(HaltReason);
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enum class Architecture {
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Aarch32,
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Aarch64,
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};
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/// Generic ARMv8 CPU interface
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/// Generic ARMv8 CPU interface
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class ARM_Interface {
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class ARM_Interface {
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public:
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public:
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@ -167,8 +181,9 @@ public:
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*/
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*/
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virtual void SetTPIDR_EL0(u64 value) = 0;
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virtual void SetTPIDR_EL0(u64 value) = 0;
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virtual void SaveContext(ThreadContext32& ctx) = 0;
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virtual Architecture GetArchitecture() const = 0;
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virtual void SaveContext(ThreadContext64& ctx) = 0;
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virtual void SaveContext(ThreadContext32& ctx) const = 0;
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virtual void SaveContext(ThreadContext64& ctx) const = 0;
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virtual void LoadContext(const ThreadContext32& ctx) = 0;
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virtual void LoadContext(const ThreadContext32& ctx) = 0;
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virtual void LoadContext(const ThreadContext64& ctx) = 0;
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virtual void LoadContext(const ThreadContext64& ctx) = 0;
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void LoadWatchpointArray(const WatchpointArray& wp);
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void LoadWatchpointArray(const WatchpointArray& wp);
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@ -195,17 +210,9 @@ public:
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static std::vector<BacktraceEntry> GetBacktraceFromContext(System& system,
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static std::vector<BacktraceEntry> GetBacktraceFromContext(System& system,
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const ThreadContext64& ctx);
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const ThreadContext64& ctx);
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virtual std::vector<BacktraceEntry> GetBacktrace() const = 0;
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std::vector<BacktraceEntry> GetBacktrace() const;
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void LogBacktrace() const;
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void LogBacktrace() const;
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static constexpr Dynarmic::HaltReason step_thread = Dynarmic::HaltReason::Step;
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static constexpr Dynarmic::HaltReason break_loop = Dynarmic::HaltReason::UserDefined2;
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static constexpr Dynarmic::HaltReason svc_call = Dynarmic::HaltReason::UserDefined3;
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static constexpr Dynarmic::HaltReason breakpoint = Dynarmic::HaltReason::UserDefined4;
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static constexpr Dynarmic::HaltReason watchpoint = Dynarmic::HaltReason::MemoryAbort;
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static constexpr Dynarmic::HaltReason no_execute = Dynarmic::HaltReason::UserDefined6;
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protected:
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protected:
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/// System context that this ARM interface is running under.
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/// System context that this ARM interface is running under.
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System& system;
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System& system;
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@ -216,8 +223,8 @@ protected:
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const Kernel::DebugWatchpoint* MatchingWatchpoint(
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const Kernel::DebugWatchpoint* MatchingWatchpoint(
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u64 addr, u64 size, Kernel::DebugWatchpointType access_type) const;
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u64 addr, u64 size, Kernel::DebugWatchpointType access_type) const;
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virtual Dynarmic::HaltReason RunJit() = 0;
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virtual HaltReason RunJit() = 0;
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virtual Dynarmic::HaltReason StepJit() = 0;
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virtual HaltReason StepJit() = 0;
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virtual u32 GetSvcNumber() const = 0;
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virtual u32 GetSvcNumber() const = 0;
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virtual const Kernel::DebugWatchpoint* HaltedWatchpoint() const = 0;
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virtual const Kernel::DebugWatchpoint* HaltedWatchpoint() const = 0;
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virtual void RewindBreakpointInstruction() = 0;
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virtual void RewindBreakpointInstruction() = 0;
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29
src/core/arm/dynarmic/arm_dynarmic.h
Executable file
29
src/core/arm/dynarmic/arm_dynarmic.h
Executable file
@ -0,0 +1,29 @@
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <dynarmic/interface/halt_reason.h>
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#include "core/arm/arm_interface.h"
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namespace Core {
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constexpr Dynarmic::HaltReason StepThread = Dynarmic::HaltReason::Step;
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constexpr Dynarmic::HaltReason DataAbort = Dynarmic::HaltReason::MemoryAbort;
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constexpr Dynarmic::HaltReason BreakLoop = Dynarmic::HaltReason::UserDefined2;
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constexpr Dynarmic::HaltReason SupervisorCall = Dynarmic::HaltReason::UserDefined3;
|
||||||
|
constexpr Dynarmic::HaltReason InstructionBreakpoint = Dynarmic::HaltReason::UserDefined4;
|
||||||
|
constexpr Dynarmic::HaltReason PrefetchAbort = Dynarmic::HaltReason::UserDefined6;
|
||||||
|
|
||||||
|
constexpr HaltReason TranslateHaltReason(Dynarmic::HaltReason hr) {
|
||||||
|
static_assert(static_cast<u64>(HaltReason::StepThread) == static_cast<u64>(StepThread));
|
||||||
|
static_assert(static_cast<u64>(HaltReason::DataAbort) == static_cast<u64>(DataAbort));
|
||||||
|
static_assert(static_cast<u64>(HaltReason::BreakLoop) == static_cast<u64>(BreakLoop));
|
||||||
|
static_assert(static_cast<u64>(HaltReason::SupervisorCall) == static_cast<u64>(SupervisorCall));
|
||||||
|
static_assert(static_cast<u64>(HaltReason::InstructionBreakpoint) ==
|
||||||
|
static_cast<u64>(InstructionBreakpoint));
|
||||||
|
static_assert(static_cast<u64>(HaltReason::PrefetchAbort) == static_cast<u64>(PrefetchAbort));
|
||||||
|
|
||||||
|
return static_cast<HaltReason>(hr);
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace Core
|
@ -10,9 +10,10 @@
|
|||||||
#include "common/logging/log.h"
|
#include "common/logging/log.h"
|
||||||
#include "common/page_table.h"
|
#include "common/page_table.h"
|
||||||
#include "common/settings.h"
|
#include "common/settings.h"
|
||||||
|
#include "core/arm/dynarmic/arm_dynarmic.h"
|
||||||
#include "core/arm/dynarmic/arm_dynarmic_32.h"
|
#include "core/arm/dynarmic/arm_dynarmic_32.h"
|
||||||
#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
|
#include "core/arm/dynarmic/dynarmic_cp15.h"
|
||||||
#include "core/arm/dynarmic/arm_exclusive_monitor.h"
|
#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
|
||||||
#include "core/core.h"
|
#include "core/core.h"
|
||||||
#include "core/core_timing.h"
|
#include "core/core_timing.h"
|
||||||
#include "core/debugger/debugger.h"
|
#include "core/debugger/debugger.h"
|
||||||
@ -104,11 +105,11 @@ public:
|
|||||||
switch (exception) {
|
switch (exception) {
|
||||||
case Dynarmic::A32::Exception::NoExecuteFault:
|
case Dynarmic::A32::Exception::NoExecuteFault:
|
||||||
LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#08x}", pc);
|
LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#08x}", pc);
|
||||||
ReturnException(pc, ARM_Interface::no_execute);
|
ReturnException(pc, PrefetchAbort);
|
||||||
return;
|
return;
|
||||||
default:
|
default:
|
||||||
if (debugger_enabled) {
|
if (debugger_enabled) {
|
||||||
ReturnException(pc, ARM_Interface::breakpoint);
|
ReturnException(pc, InstructionBreakpoint);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -121,7 +122,7 @@ public:
|
|||||||
|
|
||||||
void CallSVC(u32 swi) override {
|
void CallSVC(u32 swi) override {
|
||||||
parent.svc_swi = swi;
|
parent.svc_swi = swi;
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::svc_call);
|
parent.jit.load()->HaltExecution(SupervisorCall);
|
||||||
}
|
}
|
||||||
|
|
||||||
void AddTicks(u64 ticks) override {
|
void AddTicks(u64 ticks) override {
|
||||||
@ -162,7 +163,7 @@ public:
|
|||||||
if (!memory.IsValidVirtualAddressRange(addr, size)) {
|
if (!memory.IsValidVirtualAddressRange(addr, size)) {
|
||||||
LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
|
LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
|
||||||
addr);
|
addr);
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::no_execute);
|
parent.jit.load()->HaltExecution(PrefetchAbort);
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -173,7 +174,7 @@ public:
|
|||||||
const auto match{parent.MatchingWatchpoint(addr, size, type)};
|
const auto match{parent.MatchingWatchpoint(addr, size, type)};
|
||||||
if (match) {
|
if (match) {
|
||||||
parent.halted_watchpoint = match;
|
parent.halted_watchpoint = match;
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::watchpoint);
|
parent.jit.load()->HaltExecution(DataAbort);
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -329,12 +330,12 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
|
|||||||
return std::make_unique<Dynarmic::A32::Jit>(config);
|
return std::make_unique<Dynarmic::A32::Jit>(config);
|
||||||
}
|
}
|
||||||
|
|
||||||
Dynarmic::HaltReason ARM_Dynarmic_32::RunJit() {
|
HaltReason ARM_Dynarmic_32::RunJit() {
|
||||||
return jit.load()->Run();
|
return TranslateHaltReason(jit.load()->Run());
|
||||||
}
|
}
|
||||||
|
|
||||||
Dynarmic::HaltReason ARM_Dynarmic_32::StepJit() {
|
HaltReason ARM_Dynarmic_32::StepJit() {
|
||||||
return jit.load()->Step();
|
return TranslateHaltReason(jit.load()->Step());
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 ARM_Dynarmic_32::GetSvcNumber() const {
|
u32 ARM_Dynarmic_32::GetSvcNumber() const {
|
||||||
@ -408,7 +409,7 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
|
|||||||
cp15->uprw = static_cast<u32>(value);
|
cp15->uprw = static_cast<u32>(value);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
|
void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) const {
|
||||||
Dynarmic::A32::Jit* j = jit.load();
|
Dynarmic::A32::Jit* j = jit.load();
|
||||||
ctx.cpu_registers = j->Regs();
|
ctx.cpu_registers = j->Regs();
|
||||||
ctx.extension_registers = j->ExtRegs();
|
ctx.extension_registers = j->ExtRegs();
|
||||||
@ -425,11 +426,11 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_32::SignalInterrupt() {
|
void ARM_Dynarmic_32::SignalInterrupt() {
|
||||||
jit.load()->HaltExecution(break_loop);
|
jit.load()->HaltExecution(BreakLoop);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_32::ClearInterrupt() {
|
void ARM_Dynarmic_32::ClearInterrupt() {
|
||||||
jit.load()->ClearHalt(break_loop);
|
jit.load()->ClearHalt(BreakLoop);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_32::ClearInstructionCache() {
|
void ARM_Dynarmic_32::ClearInstructionCache() {
|
||||||
@ -462,39 +463,4 @@ void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
|
|||||||
jit_cache.emplace(key, std::move(new_jit));
|
jit_cache.emplace(key, std::move(new_jit));
|
||||||
}
|
}
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_32::GetBacktrace(Core::System& system,
|
|
||||||
u64 fp, u64 lr, u64 pc) {
|
|
||||||
std::vector<BacktraceEntry> out;
|
|
||||||
auto& memory = system.ApplicationMemory();
|
|
||||||
|
|
||||||
out.push_back({"", 0, pc, 0, ""});
|
|
||||||
|
|
||||||
// fp (= r11) points to the last frame record.
|
|
||||||
// Frame records are two words long:
|
|
||||||
// fp+0 : pointer to previous frame record
|
|
||||||
// fp+4 : value of lr for frame
|
|
||||||
for (size_t i = 0; i < 256; i++) {
|
|
||||||
out.push_back({"", 0, lr, 0, ""});
|
|
||||||
if (!fp || (fp % 4 != 0) || !memory.IsValidVirtualAddressRange(fp, 8)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
lr = memory.Read32(fp + 4);
|
|
||||||
fp = memory.Read32(fp);
|
|
||||||
}
|
|
||||||
|
|
||||||
SymbolicateBacktrace(system, out);
|
|
||||||
|
|
||||||
return out;
|
|
||||||
}
|
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_32::GetBacktraceFromContext(
|
|
||||||
System& system, const ThreadContext32& ctx) {
|
|
||||||
const auto& reg = ctx.cpu_registers;
|
|
||||||
return GetBacktrace(system, reg[11], reg[14], reg[15]);
|
|
||||||
}
|
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_32::GetBacktrace() const {
|
|
||||||
return GetBacktrace(system, GetReg(11), GetReg(14), GetReg(15));
|
|
||||||
}
|
|
||||||
|
|
||||||
} // namespace Core
|
} // namespace Core
|
||||||
|
@ -50,8 +50,11 @@ public:
|
|||||||
return (GetPSTATE() & 0x20) != 0;
|
return (GetPSTATE() & 0x20) != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void SaveContext(ThreadContext32& ctx) override;
|
Architecture GetArchitecture() const override {
|
||||||
void SaveContext(ThreadContext64& ctx) override {}
|
return Architecture::Aarch32;
|
||||||
|
}
|
||||||
|
void SaveContext(ThreadContext32& ctx) const override;
|
||||||
|
void SaveContext(ThreadContext64& ctx) const override {}
|
||||||
void LoadContext(const ThreadContext32& ctx) override;
|
void LoadContext(const ThreadContext32& ctx) override;
|
||||||
void LoadContext(const ThreadContext64& ctx) override {}
|
void LoadContext(const ThreadContext64& ctx) override {}
|
||||||
|
|
||||||
@ -64,14 +67,9 @@ public:
|
|||||||
void PageTableChanged(Common::PageTable& new_page_table,
|
void PageTableChanged(Common::PageTable& new_page_table,
|
||||||
std::size_t new_address_space_size_in_bits) override;
|
std::size_t new_address_space_size_in_bits) override;
|
||||||
|
|
||||||
static std::vector<BacktraceEntry> GetBacktraceFromContext(System& system,
|
|
||||||
const ThreadContext32& ctx);
|
|
||||||
|
|
||||||
std::vector<BacktraceEntry> GetBacktrace() const override;
|
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
Dynarmic::HaltReason RunJit() override;
|
HaltReason RunJit() override;
|
||||||
Dynarmic::HaltReason StepJit() override;
|
HaltReason StepJit() override;
|
||||||
u32 GetSvcNumber() const override;
|
u32 GetSvcNumber() const override;
|
||||||
const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
|
const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
|
||||||
void RewindBreakpointInstruction() override;
|
void RewindBreakpointInstruction() override;
|
||||||
|
@ -10,8 +10,9 @@
|
|||||||
#include "common/logging/log.h"
|
#include "common/logging/log.h"
|
||||||
#include "common/page_table.h"
|
#include "common/page_table.h"
|
||||||
#include "common/settings.h"
|
#include "common/settings.h"
|
||||||
|
#include "core/arm/dynarmic/arm_dynarmic.h"
|
||||||
#include "core/arm/dynarmic/arm_dynarmic_64.h"
|
#include "core/arm/dynarmic/arm_dynarmic_64.h"
|
||||||
#include "core/arm/dynarmic/arm_exclusive_monitor.h"
|
#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
|
||||||
#include "core/core.h"
|
#include "core/core.h"
|
||||||
#include "core/core_timing.h"
|
#include "core/core_timing.h"
|
||||||
#include "core/debugger/debugger.h"
|
#include "core/debugger/debugger.h"
|
||||||
@ -113,7 +114,7 @@ public:
|
|||||||
LOG_ERROR(Core_ARM,
|
LOG_ERROR(Core_ARM,
|
||||||
"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
|
"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
|
||||||
num_instructions, memory.Read32(pc));
|
num_instructions, memory.Read32(pc));
|
||||||
ReturnException(pc, ARM_Interface::no_execute);
|
ReturnException(pc, PrefetchAbort);
|
||||||
}
|
}
|
||||||
|
|
||||||
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
|
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
|
||||||
@ -148,11 +149,11 @@ public:
|
|||||||
return;
|
return;
|
||||||
case Dynarmic::A64::Exception::NoExecuteFault:
|
case Dynarmic::A64::Exception::NoExecuteFault:
|
||||||
LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#016x}", pc);
|
LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#016x}", pc);
|
||||||
ReturnException(pc, ARM_Interface::no_execute);
|
ReturnException(pc, PrefetchAbort);
|
||||||
return;
|
return;
|
||||||
default:
|
default:
|
||||||
if (debugger_enabled) {
|
if (debugger_enabled) {
|
||||||
ReturnException(pc, ARM_Interface::breakpoint);
|
ReturnException(pc, InstructionBreakpoint);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -164,7 +165,7 @@ public:
|
|||||||
|
|
||||||
void CallSVC(u32 swi) override {
|
void CallSVC(u32 swi) override {
|
||||||
parent.svc_swi = swi;
|
parent.svc_swi = swi;
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::svc_call);
|
parent.jit.load()->HaltExecution(SupervisorCall);
|
||||||
}
|
}
|
||||||
|
|
||||||
void AddTicks(u64 ticks) override {
|
void AddTicks(u64 ticks) override {
|
||||||
@ -207,7 +208,7 @@ public:
|
|||||||
if (!memory.IsValidVirtualAddressRange(addr, size)) {
|
if (!memory.IsValidVirtualAddressRange(addr, size)) {
|
||||||
LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
|
LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
|
||||||
addr);
|
addr);
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::no_execute);
|
parent.jit.load()->HaltExecution(PrefetchAbort);
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -218,7 +219,7 @@ public:
|
|||||||
const auto match{parent.MatchingWatchpoint(addr, size, type)};
|
const auto match{parent.MatchingWatchpoint(addr, size, type)};
|
||||||
if (match) {
|
if (match) {
|
||||||
parent.halted_watchpoint = match;
|
parent.halted_watchpoint = match;
|
||||||
parent.jit.load()->HaltExecution(ARM_Interface::watchpoint);
|
parent.jit.load()->HaltExecution(DataAbort);
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -383,12 +384,12 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
|
|||||||
return std::make_shared<Dynarmic::A64::Jit>(config);
|
return std::make_shared<Dynarmic::A64::Jit>(config);
|
||||||
}
|
}
|
||||||
|
|
||||||
Dynarmic::HaltReason ARM_Dynarmic_64::RunJit() {
|
HaltReason ARM_Dynarmic_64::RunJit() {
|
||||||
return jit.load()->Run();
|
return TranslateHaltReason(jit.load()->Run());
|
||||||
}
|
}
|
||||||
|
|
||||||
Dynarmic::HaltReason ARM_Dynarmic_64::StepJit() {
|
HaltReason ARM_Dynarmic_64::StepJit() {
|
||||||
return jit.load()->Step();
|
return TranslateHaltReason(jit.load()->Step());
|
||||||
}
|
}
|
||||||
|
|
||||||
u32 ARM_Dynarmic_64::GetSvcNumber() const {
|
u32 ARM_Dynarmic_64::GetSvcNumber() const {
|
||||||
@ -464,7 +465,7 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
|
|||||||
cb->tpidr_el0 = value;
|
cb->tpidr_el0 = value;
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
|
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) const {
|
||||||
Dynarmic::A64::Jit* j = jit.load();
|
Dynarmic::A64::Jit* j = jit.load();
|
||||||
ctx.cpu_registers = j->GetRegisters();
|
ctx.cpu_registers = j->GetRegisters();
|
||||||
ctx.sp = j->GetSP();
|
ctx.sp = j->GetSP();
|
||||||
@ -489,11 +490,11 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_64::SignalInterrupt() {
|
void ARM_Dynarmic_64::SignalInterrupt() {
|
||||||
jit.load()->HaltExecution(break_loop);
|
jit.load()->HaltExecution(BreakLoop);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_64::ClearInterrupt() {
|
void ARM_Dynarmic_64::ClearInterrupt() {
|
||||||
jit.load()->ClearHalt(break_loop);
|
jit.load()->ClearHalt(BreakLoop);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM_Dynarmic_64::ClearInstructionCache() {
|
void ARM_Dynarmic_64::ClearInstructionCache() {
|
||||||
@ -526,39 +527,4 @@ void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
|
|||||||
jit_cache.emplace(key, std::move(new_jit));
|
jit_cache.emplace(key, std::move(new_jit));
|
||||||
}
|
}
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktrace(Core::System& system,
|
|
||||||
u64 fp, u64 lr, u64 pc) {
|
|
||||||
std::vector<BacktraceEntry> out;
|
|
||||||
auto& memory = system.ApplicationMemory();
|
|
||||||
|
|
||||||
out.push_back({"", 0, pc, 0, ""});
|
|
||||||
|
|
||||||
// fp (= x29) points to the previous frame record.
|
|
||||||
// Frame records are two words long:
|
|
||||||
// fp+0 : pointer to previous frame record
|
|
||||||
// fp+8 : value of lr for frame
|
|
||||||
for (size_t i = 0; i < 256; i++) {
|
|
||||||
out.push_back({"", 0, lr, 0, ""});
|
|
||||||
if (!fp || (fp % 4 != 0) || !memory.IsValidVirtualAddressRange(fp, 16)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
lr = memory.Read64(fp + 8);
|
|
||||||
fp = memory.Read64(fp);
|
|
||||||
}
|
|
||||||
|
|
||||||
SymbolicateBacktrace(system, out);
|
|
||||||
|
|
||||||
return out;
|
|
||||||
}
|
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktraceFromContext(
|
|
||||||
System& system, const ThreadContext64& ctx) {
|
|
||||||
const auto& reg = ctx.cpu_registers;
|
|
||||||
return GetBacktrace(system, reg[29], reg[30], ctx.pc);
|
|
||||||
}
|
|
||||||
|
|
||||||
std::vector<ARM_Interface::BacktraceEntry> ARM_Dynarmic_64::GetBacktrace() const {
|
|
||||||
return GetBacktrace(system, GetReg(29), GetReg(30), GetPC());
|
|
||||||
}
|
|
||||||
|
|
||||||
} // namespace Core
|
} // namespace Core
|
||||||
|
@ -43,8 +43,11 @@ public:
|
|||||||
void SetTPIDR_EL0(u64 value) override;
|
void SetTPIDR_EL0(u64 value) override;
|
||||||
u64 GetTPIDR_EL0() const override;
|
u64 GetTPIDR_EL0() const override;
|
||||||
|
|
||||||
void SaveContext(ThreadContext32& ctx) override {}
|
Architecture GetArchitecture() const override {
|
||||||
void SaveContext(ThreadContext64& ctx) override;
|
return Architecture::Aarch64;
|
||||||
|
}
|
||||||
|
void SaveContext(ThreadContext32& ctx) const override {}
|
||||||
|
void SaveContext(ThreadContext64& ctx) const override;
|
||||||
void LoadContext(const ThreadContext32& ctx) override {}
|
void LoadContext(const ThreadContext32& ctx) override {}
|
||||||
void LoadContext(const ThreadContext64& ctx) override;
|
void LoadContext(const ThreadContext64& ctx) override;
|
||||||
|
|
||||||
@ -57,14 +60,9 @@ public:
|
|||||||
void PageTableChanged(Common::PageTable& new_page_table,
|
void PageTableChanged(Common::PageTable& new_page_table,
|
||||||
std::size_t new_address_space_size_in_bits) override;
|
std::size_t new_address_space_size_in_bits) override;
|
||||||
|
|
||||||
static std::vector<BacktraceEntry> GetBacktraceFromContext(System& system,
|
|
||||||
const ThreadContext64& ctx);
|
|
||||||
|
|
||||||
std::vector<BacktraceEntry> GetBacktrace() const override;
|
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
Dynarmic::HaltReason RunJit() override;
|
HaltReason RunJit() override;
|
||||||
Dynarmic::HaltReason StepJit() override;
|
HaltReason StepJit() override;
|
||||||
u32 GetSvcNumber() const override;
|
u32 GetSvcNumber() const override;
|
||||||
const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
|
const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
|
||||||
void RewindBreakpointInstruction() override;
|
void RewindBreakpointInstruction() override;
|
||||||
@ -73,8 +71,6 @@ private:
|
|||||||
std::shared_ptr<Dynarmic::A64::Jit> MakeJit(Common::PageTable* page_table,
|
std::shared_ptr<Dynarmic::A64::Jit> MakeJit(Common::PageTable* page_table,
|
||||||
std::size_t address_space_bits) const;
|
std::size_t address_space_bits) const;
|
||||||
|
|
||||||
static std::vector<BacktraceEntry> GetBacktrace(Core::System& system, u64 fp, u64 lr, u64 pc);
|
|
||||||
|
|
||||||
using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
|
using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
|
||||||
using JitCacheType =
|
using JitCacheType =
|
||||||
std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A64::Jit>, Common::PairHash>;
|
std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A64::Jit>, Common::PairHash>;
|
||||||
|
161
src/core/arm/dynarmic/dynarmic_cp15.cpp
Executable file
161
src/core/arm/dynarmic/dynarmic_cp15.cpp
Executable file
@ -0,0 +1,161 @@
|
|||||||
|
// SPDX-FileCopyrightText: 2017 Citra Emulator Project
|
||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#include <fmt/format.h>
|
||||||
|
#include "common/logging/log.h"
|
||||||
|
#include "core/arm/dynarmic/arm_dynarmic_32.h"
|
||||||
|
#include "core/arm/dynarmic/dynarmic_cp15.h"
|
||||||
|
#include "core/core.h"
|
||||||
|
#include "core/core_timing.h"
|
||||||
|
|
||||||
|
#ifdef _MSC_VER
|
||||||
|
#include <intrin.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
using Callback = Dynarmic::A32::Coprocessor::Callback;
|
||||||
|
using CallbackOrAccessOneWord = Dynarmic::A32::Coprocessor::CallbackOrAccessOneWord;
|
||||||
|
using CallbackOrAccessTwoWords = Dynarmic::A32::Coprocessor::CallbackOrAccessTwoWords;
|
||||||
|
|
||||||
|
template <>
|
||||||
|
struct fmt::formatter<Dynarmic::A32::CoprocReg> {
|
||||||
|
constexpr auto parse(format_parse_context& ctx) {
|
||||||
|
return ctx.begin();
|
||||||
|
}
|
||||||
|
template <typename FormatContext>
|
||||||
|
auto format(const Dynarmic::A32::CoprocReg& reg, FormatContext& ctx) {
|
||||||
|
return fmt::format_to(ctx.out(), "cp{}", static_cast<size_t>(reg));
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
namespace Core {
|
||||||
|
|
||||||
|
static u32 dummy_value;
|
||||||
|
|
||||||
|
std::optional<Callback> DynarmicCP15::CompileInternalOperation(bool two, unsigned opc1,
|
||||||
|
CoprocReg CRd, CoprocReg CRn,
|
||||||
|
CoprocReg CRm, unsigned opc2) {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: cdp{} p15, {}, {}, {}, {}, {}", two ? "2" : "", opc1, CRd, CRn,
|
||||||
|
CRm, opc2);
|
||||||
|
return std::nullopt;
|
||||||
|
}
|
||||||
|
|
||||||
|
CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1, CoprocReg CRn,
|
||||||
|
CoprocReg CRm, unsigned opc2) {
|
||||||
|
if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C5 && opc2 == 4) {
|
||||||
|
// CP15_FLUSH_PREFETCH_BUFFER
|
||||||
|
// This is a dummy write, we ignore the value written here.
|
||||||
|
return &dummy_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C10) {
|
||||||
|
switch (opc2) {
|
||||||
|
case 4:
|
||||||
|
// CP15_DATA_SYNC_BARRIER
|
||||||
|
return Callback{
|
||||||
|
[](void*, std::uint32_t, std::uint32_t) -> std::uint64_t {
|
||||||
|
#if defined(_MSC_VER) && defined(ARCHITECTURE_x86_64)
|
||||||
|
_mm_mfence();
|
||||||
|
_mm_lfence();
|
||||||
|
#elif defined(ARCHITECTURE_x86_64)
|
||||||
|
asm volatile("mfence\n\tlfence\n\t" : : : "memory");
|
||||||
|
#elif defined(ARCHITECTURE_arm64)
|
||||||
|
asm volatile("dsb sy\n\t" : : : "memory");
|
||||||
|
#else
|
||||||
|
#error Unsupported architecture
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
},
|
||||||
|
std::nullopt,
|
||||||
|
};
|
||||||
|
case 5:
|
||||||
|
// CP15_DATA_MEMORY_BARRIER
|
||||||
|
return Callback{
|
||||||
|
[](void*, std::uint32_t, std::uint32_t) -> std::uint64_t {
|
||||||
|
#if defined(_MSC_VER) && defined(ARCHITECTURE_x86_64)
|
||||||
|
_mm_mfence();
|
||||||
|
#elif defined(ARCHITECTURE_x86_64)
|
||||||
|
asm volatile("mfence\n\t" : : : "memory");
|
||||||
|
#elif defined(ARCHITECTURE_arm64)
|
||||||
|
asm volatile("dmb sy\n\t" : : : "memory");
|
||||||
|
#else
|
||||||
|
#error Unsupported architecture
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
},
|
||||||
|
std::nullopt,
|
||||||
|
};
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0 && opc2 == 2) {
|
||||||
|
// CP15_THREAD_UPRW
|
||||||
|
return &uprw;
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mcr{} p15, {}, <Rt>, {}, {}, {}", two ? "2" : "", opc1, CRn, CRm,
|
||||||
|
opc2);
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
|
CallbackOrAccessTwoWords DynarmicCP15::CompileSendTwoWords(bool two, unsigned opc, CoprocReg CRm) {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mcrr{} p15, {}, <Rt>, <Rt2>, {}", two ? "2" : "", opc, CRm);
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
|
CallbackOrAccessOneWord DynarmicCP15::CompileGetOneWord(bool two, unsigned opc1, CoprocReg CRn,
|
||||||
|
CoprocReg CRm, unsigned opc2) {
|
||||||
|
if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0) {
|
||||||
|
switch (opc2) {
|
||||||
|
case 2:
|
||||||
|
// CP15_THREAD_UPRW
|
||||||
|
return &uprw;
|
||||||
|
case 3:
|
||||||
|
// CP15_THREAD_URO
|
||||||
|
return &uro;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrc{} p15, {}, <Rt>, {}, {}, {}", two ? "2" : "", opc1, CRn, CRm,
|
||||||
|
opc2);
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
|
CallbackOrAccessTwoWords DynarmicCP15::CompileGetTwoWords(bool two, unsigned opc, CoprocReg CRm) {
|
||||||
|
if (!two && opc == 0 && CRm == CoprocReg::C14) {
|
||||||
|
// CNTPCT
|
||||||
|
const auto callback = [](void* arg, u32, u32) -> u64 {
|
||||||
|
const auto& parent_arg = *static_cast<ARM_Dynarmic_32*>(arg);
|
||||||
|
return parent_arg.system.CoreTiming().GetClockTicks();
|
||||||
|
};
|
||||||
|
return Callback{callback, &parent};
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrrc{} p15, {}, <Rt>, <Rt2>, {}", two ? "2" : "", opc, CRm);
|
||||||
|
return {};
|
||||||
|
}
|
||||||
|
|
||||||
|
std::optional<Callback> DynarmicCP15::CompileLoadWords(bool two, bool long_transfer, CoprocReg CRd,
|
||||||
|
std::optional<u8> option) {
|
||||||
|
if (option) {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...], {}", two ? "2" : "",
|
||||||
|
long_transfer ? "l" : "", CRd, *option);
|
||||||
|
} else {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...]", two ? "2" : "",
|
||||||
|
long_transfer ? "l" : "", CRd);
|
||||||
|
}
|
||||||
|
return std::nullopt;
|
||||||
|
}
|
||||||
|
|
||||||
|
std::optional<Callback> DynarmicCP15::CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
|
||||||
|
std::optional<u8> option) {
|
||||||
|
if (option) {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...], {}", two ? "2" : "",
|
||||||
|
long_transfer ? "l" : "", CRd, *option);
|
||||||
|
} else {
|
||||||
|
LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...]", two ? "2" : "",
|
||||||
|
long_transfer ? "l" : "", CRd);
|
||||||
|
}
|
||||||
|
return std::nullopt;
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace Core
|
42
src/core/arm/dynarmic/dynarmic_cp15.h
Executable file
42
src/core/arm/dynarmic/dynarmic_cp15.h
Executable file
@ -0,0 +1,42 @@
|
|||||||
|
// SPDX-FileCopyrightText: 2017 Citra Emulator Project
|
||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include <optional>
|
||||||
|
|
||||||
|
#include <dynarmic/interface/A32/coprocessor.h>
|
||||||
|
#include "common/common_types.h"
|
||||||
|
|
||||||
|
namespace Core {
|
||||||
|
|
||||||
|
class ARM_Dynarmic_32;
|
||||||
|
|
||||||
|
class DynarmicCP15 final : public Dynarmic::A32::Coprocessor {
|
||||||
|
public:
|
||||||
|
using CoprocReg = Dynarmic::A32::CoprocReg;
|
||||||
|
|
||||||
|
explicit DynarmicCP15(ARM_Dynarmic_32& parent_) : parent{parent_} {}
|
||||||
|
|
||||||
|
std::optional<Callback> CompileInternalOperation(bool two, unsigned opc1, CoprocReg CRd,
|
||||||
|
CoprocReg CRn, CoprocReg CRm,
|
||||||
|
unsigned opc2) override;
|
||||||
|
CallbackOrAccessOneWord CompileSendOneWord(bool two, unsigned opc1, CoprocReg CRn,
|
||||||
|
CoprocReg CRm, unsigned opc2) override;
|
||||||
|
CallbackOrAccessTwoWords CompileSendTwoWords(bool two, unsigned opc, CoprocReg CRm) override;
|
||||||
|
CallbackOrAccessOneWord CompileGetOneWord(bool two, unsigned opc1, CoprocReg CRn, CoprocReg CRm,
|
||||||
|
unsigned opc2) override;
|
||||||
|
CallbackOrAccessTwoWords CompileGetTwoWords(bool two, unsigned opc, CoprocReg CRm) override;
|
||||||
|
std::optional<Callback> CompileLoadWords(bool two, bool long_transfer, CoprocReg CRd,
|
||||||
|
std::optional<u8> option) override;
|
||||||
|
std::optional<Callback> CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
|
||||||
|
std::optional<u8> option) override;
|
||||||
|
|
||||||
|
ARM_Dynarmic_32& parent;
|
||||||
|
u32 uprw = 0;
|
||||||
|
u32 uro = 0;
|
||||||
|
|
||||||
|
friend class ARM_Dynarmic_32;
|
||||||
|
};
|
||||||
|
|
||||||
|
} // namespace Core
|
73
src/core/arm/dynarmic/dynarmic_exclusive_monitor.cpp
Executable file
73
src/core/arm/dynarmic/dynarmic_exclusive_monitor.cpp
Executable file
@ -0,0 +1,73 @@
|
|||||||
|
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
|
||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
|
||||||
|
#include "core/memory.h"
|
||||||
|
|
||||||
|
namespace Core {
|
||||||
|
|
||||||
|
DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(Memory::Memory& memory_, std::size_t core_count_)
|
||||||
|
: monitor{core_count_}, memory{memory_} {}
|
||||||
|
|
||||||
|
DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
|
||||||
|
|
||||||
|
u8 DynarmicExclusiveMonitor::ExclusiveRead8(std::size_t core_index, VAddr addr) {
|
||||||
|
return monitor.ReadAndMark<u8>(core_index, addr, [&]() -> u8 { return memory.Read8(addr); });
|
||||||
|
}
|
||||||
|
|
||||||
|
u16 DynarmicExclusiveMonitor::ExclusiveRead16(std::size_t core_index, VAddr addr) {
|
||||||
|
return monitor.ReadAndMark<u16>(core_index, addr, [&]() -> u16 { return memory.Read16(addr); });
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 DynarmicExclusiveMonitor::ExclusiveRead32(std::size_t core_index, VAddr addr) {
|
||||||
|
return monitor.ReadAndMark<u32>(core_index, addr, [&]() -> u32 { return memory.Read32(addr); });
|
||||||
|
}
|
||||||
|
|
||||||
|
u64 DynarmicExclusiveMonitor::ExclusiveRead64(std::size_t core_index, VAddr addr) {
|
||||||
|
return monitor.ReadAndMark<u64>(core_index, addr, [&]() -> u64 { return memory.Read64(addr); });
|
||||||
|
}
|
||||||
|
|
||||||
|
u128 DynarmicExclusiveMonitor::ExclusiveRead128(std::size_t core_index, VAddr addr) {
|
||||||
|
return monitor.ReadAndMark<u128>(core_index, addr, [&]() -> u128 {
|
||||||
|
u128 result;
|
||||||
|
result[0] = memory.Read64(addr);
|
||||||
|
result[1] = memory.Read64(addr + 8);
|
||||||
|
return result;
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
void DynarmicExclusiveMonitor::ClearExclusive(std::size_t core_index) {
|
||||||
|
monitor.ClearProcessor(core_index);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
|
||||||
|
return monitor.DoExclusiveOperation<u8>(core_index, vaddr, [&](u8 expected) -> bool {
|
||||||
|
return memory.WriteExclusive8(vaddr, value, expected);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
|
||||||
|
return monitor.DoExclusiveOperation<u16>(core_index, vaddr, [&](u16 expected) -> bool {
|
||||||
|
return memory.WriteExclusive16(vaddr, value, expected);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
|
||||||
|
return monitor.DoExclusiveOperation<u32>(core_index, vaddr, [&](u32 expected) -> bool {
|
||||||
|
return memory.WriteExclusive32(vaddr, value, expected);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
|
||||||
|
return monitor.DoExclusiveOperation<u64>(core_index, vaddr, [&](u64 expected) -> bool {
|
||||||
|
return memory.WriteExclusive64(vaddr, value, expected);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
|
||||||
|
return monitor.DoExclusiveOperation<u128>(core_index, vaddr, [&](u128 expected) -> bool {
|
||||||
|
return memory.WriteExclusive128(vaddr, value, expected);
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace Core
|
44
src/core/arm/dynarmic/dynarmic_exclusive_monitor.h
Executable file
44
src/core/arm/dynarmic/dynarmic_exclusive_monitor.h
Executable file
@ -0,0 +1,44 @@
|
|||||||
|
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include <dynarmic/interface/exclusive_monitor.h>
|
||||||
|
|
||||||
|
#include "common/common_types.h"
|
||||||
|
#include "core/arm/dynarmic/arm_dynarmic_32.h"
|
||||||
|
#include "core/arm/dynarmic/arm_dynarmic_64.h"
|
||||||
|
#include "core/arm/exclusive_monitor.h"
|
||||||
|
|
||||||
|
namespace Core::Memory {
|
||||||
|
class Memory;
|
||||||
|
}
|
||||||
|
|
||||||
|
namespace Core {
|
||||||
|
|
||||||
|
class DynarmicExclusiveMonitor final : public ExclusiveMonitor {
|
||||||
|
public:
|
||||||
|
explicit DynarmicExclusiveMonitor(Memory::Memory& memory_, std::size_t core_count_);
|
||||||
|
~DynarmicExclusiveMonitor() override;
|
||||||
|
|
||||||
|
u8 ExclusiveRead8(std::size_t core_index, VAddr addr) override;
|
||||||
|
u16 ExclusiveRead16(std::size_t core_index, VAddr addr) override;
|
||||||
|
u32 ExclusiveRead32(std::size_t core_index, VAddr addr) override;
|
||||||
|
u64 ExclusiveRead64(std::size_t core_index, VAddr addr) override;
|
||||||
|
u128 ExclusiveRead128(std::size_t core_index, VAddr addr) override;
|
||||||
|
void ClearExclusive(std::size_t core_index) override;
|
||||||
|
|
||||||
|
bool ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) override;
|
||||||
|
bool ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) override;
|
||||||
|
bool ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) override;
|
||||||
|
bool ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) override;
|
||||||
|
bool ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) override;
|
||||||
|
|
||||||
|
private:
|
||||||
|
friend class ARM_Dynarmic_32;
|
||||||
|
friend class ARM_Dynarmic_64;
|
||||||
|
Dynarmic::ExclusiveMonitor monitor;
|
||||||
|
Core::Memory::Memory& memory;
|
||||||
|
};
|
||||||
|
|
||||||
|
} // namespace Core
|
@ -2,7 +2,7 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
#if defined(ARCHITECTURE_x86_64) || defined(ARCHITECTURE_arm64)
|
#if defined(ARCHITECTURE_x86_64) || defined(ARCHITECTURE_arm64)
|
||||||
#include "core/arm/dynarmic/arm_exclusive_monitor.h"
|
#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
|
||||||
#endif
|
#endif
|
||||||
#include "core/arm/exclusive_monitor.h"
|
#include "core/arm/exclusive_monitor.h"
|
||||||
#include "core/memory.h"
|
#include "core/memory.h"
|
||||||
|
@ -54,10 +54,10 @@
|
|||||||
#include "video_core/renderer_base.h"
|
#include "video_core/renderer_base.h"
|
||||||
#include "video_core/video_core.h"
|
#include "video_core/video_core.h"
|
||||||
|
|
||||||
MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_CPU0, "ARM JIT", "Dynarmic CPU 0", MP_RGB(255, 64, 64));
|
MICROPROFILE_DEFINE(ARM_CPU0, "ARM", "CPU 0", MP_RGB(255, 64, 64));
|
||||||
MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_CPU1, "ARM JIT", "Dynarmic CPU 1", MP_RGB(255, 64, 64));
|
MICROPROFILE_DEFINE(ARM_CPU1, "ARM", "CPU 1", MP_RGB(255, 64, 64));
|
||||||
MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_CPU2, "ARM JIT", "Dynarmic CPU 2", MP_RGB(255, 64, 64));
|
MICROPROFILE_DEFINE(ARM_CPU2, "ARM", "CPU 2", MP_RGB(255, 64, 64));
|
||||||
MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_CPU3, "ARM JIT", "Dynarmic CPU 3", MP_RGB(255, 64, 64));
|
MICROPROFILE_DEFINE(ARM_CPU3, "ARM", "CPU 3", MP_RGB(255, 64, 64));
|
||||||
|
|
||||||
namespace Core {
|
namespace Core {
|
||||||
|
|
||||||
@ -259,10 +259,10 @@ struct System::Impl {
|
|||||||
is_powered_on = true;
|
is_powered_on = true;
|
||||||
exit_lock = false;
|
exit_lock = false;
|
||||||
|
|
||||||
microprofile_dynarmic[0] = MICROPROFILE_TOKEN(ARM_Jit_Dynarmic_CPU0);
|
microprofile_cpu[0] = MICROPROFILE_TOKEN(ARM_CPU0);
|
||||||
microprofile_dynarmic[1] = MICROPROFILE_TOKEN(ARM_Jit_Dynarmic_CPU1);
|
microprofile_cpu[1] = MICROPROFILE_TOKEN(ARM_CPU1);
|
||||||
microprofile_dynarmic[2] = MICROPROFILE_TOKEN(ARM_Jit_Dynarmic_CPU2);
|
microprofile_cpu[2] = MICROPROFILE_TOKEN(ARM_CPU2);
|
||||||
microprofile_dynarmic[3] = MICROPROFILE_TOKEN(ARM_Jit_Dynarmic_CPU3);
|
microprofile_cpu[3] = MICROPROFILE_TOKEN(ARM_CPU3);
|
||||||
|
|
||||||
LOG_DEBUG(Core, "Initialized OK");
|
LOG_DEBUG(Core, "Initialized OK");
|
||||||
|
|
||||||
@ -539,7 +539,7 @@ struct System::Impl {
|
|||||||
ExitCallback exit_callback;
|
ExitCallback exit_callback;
|
||||||
|
|
||||||
std::array<u64, Core::Hardware::NUM_CPU_CORES> dynarmic_ticks{};
|
std::array<u64, Core::Hardware::NUM_CPU_CORES> dynarmic_ticks{};
|
||||||
std::array<MicroProfileToken, Core::Hardware::NUM_CPU_CORES> microprofile_dynarmic{};
|
std::array<MicroProfileToken, Core::Hardware::NUM_CPU_CORES> microprofile_cpu{};
|
||||||
};
|
};
|
||||||
|
|
||||||
System::System() : impl{std::make_unique<Impl>(*this)} {}
|
System::System() : impl{std::make_unique<Impl>(*this)} {}
|
||||||
@ -927,14 +927,14 @@ void System::RegisterHostThread() {
|
|||||||
impl->kernel.RegisterHostThread();
|
impl->kernel.RegisterHostThread();
|
||||||
}
|
}
|
||||||
|
|
||||||
void System::EnterDynarmicProfile() {
|
void System::EnterCPUProfile() {
|
||||||
std::size_t core = impl->kernel.GetCurrentHostThreadID();
|
std::size_t core = impl->kernel.GetCurrentHostThreadID();
|
||||||
impl->dynarmic_ticks[core] = MicroProfileEnter(impl->microprofile_dynarmic[core]);
|
impl->dynarmic_ticks[core] = MicroProfileEnter(impl->microprofile_cpu[core]);
|
||||||
}
|
}
|
||||||
|
|
||||||
void System::ExitDynarmicProfile() {
|
void System::ExitCPUProfile() {
|
||||||
std::size_t core = impl->kernel.GetCurrentHostThreadID();
|
std::size_t core = impl->kernel.GetCurrentHostThreadID();
|
||||||
MicroProfileLeave(impl->microprofile_dynarmic[core], impl->dynarmic_ticks[core]);
|
MicroProfileLeave(impl->microprofile_cpu[core], impl->dynarmic_ticks[core]);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool System::IsMulticore() const {
|
bool System::IsMulticore() const {
|
||||||
|
@ -412,11 +412,11 @@ public:
|
|||||||
/// Register a host thread as an auxiliary thread.
|
/// Register a host thread as an auxiliary thread.
|
||||||
void RegisterHostThread();
|
void RegisterHostThread();
|
||||||
|
|
||||||
/// Enter Dynarmic Microprofile
|
/// Enter CPU Microprofile
|
||||||
void EnterDynarmicProfile();
|
void EnterCPUProfile();
|
||||||
|
|
||||||
/// Exit Dynarmic Microprofile
|
/// Exit CPU Microprofile
|
||||||
void ExitDynarmicProfile();
|
void ExitCPUProfile();
|
||||||
|
|
||||||
/// Tells if system is running on multicore.
|
/// Tells if system is running on multicore.
|
||||||
[[nodiscard]] bool IsMulticore() const;
|
[[nodiscard]] bool IsMulticore() const;
|
||||||
|
Loading…
Reference in New Issue
Block a user