early-access version 4110
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@@ -134,7 +134,7 @@ bool HardwareContext::InitializeForDecoder(DecoderContext& decoder_context,
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const Decoder& decoder) {
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const auto supported_types = GetSupportedDeviceTypes();
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for (const auto type : PreferredGpuDecoders) {
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// AVPixelFormat hw_pix_fmt;
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AVPixelFormat hw_pix_fmt;
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if (std::ranges::find(supported_types, type) == supported_types.end()) {
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LOG_DEBUG(HW_GPU, "{} explicitly unsupported", av_hwdevice_get_type_name(type));
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@@ -145,11 +145,10 @@ bool HardwareContext::InitializeForDecoder(DecoderContext& decoder_context,
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continue;
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}
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// Disable GPU decoding as it cannot return decode frame ordering which breaks everything.
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// if (decoder.SupportsDecodingOnDevice(&hw_pix_fmt, type)) {
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// decoder_context.InitializeHardwareDecoder(*this, hw_pix_fmt);
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// return true;
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//}
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if (decoder.SupportsDecodingOnDevice(&hw_pix_fmt, type)) {
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decoder_context.InitializeHardwareDecoder(*this, hw_pix_fmt);
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return true;
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}
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}
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LOG_INFO(HW_GPU, "Hardware decoding is disabled due to implementation issues, using CPU.");
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@@ -10,7 +10,7 @@ namespace Tegra::Host1x {
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Host1x::Host1x(Core::System& system_)
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: system{system_}, syncpoint_manager{},
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memory_manager(system.DeviceMemory()), gmmu_manager{system, memory_manager, 32, 12},
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memory_manager(system.DeviceMemory()), gmmu_manager{system, memory_manager, 32, 0, 12},
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allocator{std::make_unique<Common::FlatAllocator<u32, 0, 32>>(1 << 12)} {}
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Host1x::~Host1x() = default;
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@@ -22,11 +22,12 @@ using Tegra::Memory::GuestMemoryFlags;
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std::atomic<size_t> MemoryManager::unique_identifier_generator{};
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MemoryManager::MemoryManager(Core::System& system_, MaxwellDeviceMemoryManager& memory_,
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u64 address_space_bits_, u64 big_page_bits_, u64 page_bits_)
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u64 address_space_bits_, GPUVAddr split_address_, u64 big_page_bits_,
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u64 page_bits_)
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: system{system_}, memory{memory_}, address_space_bits{address_space_bits_},
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page_bits{page_bits_}, big_page_bits{big_page_bits_}, entries{}, big_entries{},
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page_table{address_space_bits, address_space_bits + page_bits - 38,
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page_bits != big_page_bits ? page_bits : 0},
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split_address{split_address_}, page_bits{page_bits_}, big_page_bits{big_page_bits_},
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entries{}, big_entries{}, page_table{address_space_bits, address_space_bits + page_bits - 38,
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page_bits != big_page_bits ? page_bits : 0},
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kind_map{PTEKind::INVALID}, unique_identifier{unique_identifier_generator.fetch_add(
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1, std::memory_order_acq_rel)},
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accumulator{std::make_unique<VideoCommon::InvalidationAccumulator>()} {
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@@ -48,10 +49,10 @@ MemoryManager::MemoryManager(Core::System& system_, MaxwellDeviceMemoryManager&
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entries.resize(page_table_size / 32, 0);
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}
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MemoryManager::MemoryManager(Core::System& system_, u64 address_space_bits_, u64 big_page_bits_,
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u64 page_bits_)
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: MemoryManager(system_, system_.Host1x().MemoryManager(), address_space_bits_, big_page_bits_,
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page_bits_) {}
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MemoryManager::MemoryManager(Core::System& system_, u64 address_space_bits_,
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GPUVAddr split_address_, u64 big_page_bits_, u64 page_bits_)
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: MemoryManager(system_, system_.Host1x().MemoryManager(), address_space_bits_, split_address_,
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big_page_bits_, page_bits_) {}
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MemoryManager::~MemoryManager() = default;
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@@ -36,10 +36,11 @@ namespace Tegra {
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class MemoryManager final {
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public:
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explicit MemoryManager(Core::System& system_, u64 address_space_bits_ = 40,
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u64 big_page_bits_ = 16, u64 page_bits_ = 12);
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explicit MemoryManager(Core::System& system_, MaxwellDeviceMemoryManager& memory_,
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u64 address_space_bits_ = 40, u64 big_page_bits_ = 16,
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GPUVAddr split_address = 1ULL << 34, u64 big_page_bits_ = 16,
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u64 page_bits_ = 12);
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explicit MemoryManager(Core::System& system_, MaxwellDeviceMemoryManager& memory_,
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u64 address_space_bits_ = 40, GPUVAddr split_address = 1ULL << 34,
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u64 big_page_bits_ = 16, u64 page_bits_ = 12);
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~MemoryManager();
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static constexpr bool HAS_FLUSH_INVALIDATION = true;
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@@ -194,6 +195,7 @@ private:
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MaxwellDeviceMemoryManager& memory;
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const u64 address_space_bits;
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GPUVAddr split_address;
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const u64 page_bits;
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u64 address_space_size;
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u64 page_size;
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