early-access version 3501

This commit is contained in:
pineappleEA 2023-04-07 02:00:48 +02:00
parent e900ff1ff1
commit 3ef754c1e7
16 changed files with 37 additions and 65 deletions

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@ -1,7 +1,7 @@
yuzu emulator early access
=============
This is the source code for early-access 3500.
This is the source code for early-access 3501.
## Legal Notice

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@ -126,6 +126,17 @@ else()
add_compile_options("-stdlib=libc++")
endif()
# GCC bugs
if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL "12" AND CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
# These diagnostics would be great if they worked, but are just completely broken
# and produce bogus errors on external libraries like fmt.
add_compile_options(
-Wno-array-bounds
-Wno-stringop-overread
-Wno-stringop-overflow
)
endif()
# Set file offset size to 64 bits.
#
# On modern Unixes, this is typically already the case. The lone exception is

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@ -96,10 +96,6 @@ public:
return m_node == rhs.m_node;
}
constexpr bool operator!=(const Iterator& rhs) const {
return !(*this == rhs);
}
constexpr pointer operator->() const {
return m_node;
}
@ -324,10 +320,6 @@ public:
return m_impl == rhs.m_impl;
}
constexpr bool operator!=(const Iterator& rhs) const {
return !(*this == rhs);
}
constexpr pointer operator->() const {
return Traits::GetParent(std::addressof(*m_impl));
}

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@ -116,7 +116,6 @@ public:
// Comparison operators.
constexpr bool operator==(const TypedAddress&) const = default;
constexpr bool operator!=(const TypedAddress&) const = default;
constexpr auto operator<=>(const TypedAddress&) const = default;
// For convenience, also define comparison operators versus uint64_t.
@ -124,10 +123,6 @@ public:
return m_address == rhs;
}
constexpr inline bool operator!=(uint64_t rhs) const {
return m_address != rhs;
}
// Allow getting the address explicitly, for use in accessors.
constexpr inline uint64_t GetValue() const {
return m_address;

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@ -16,9 +16,6 @@ namespace Network {
class ProxySocket : public SocketBase {
public:
YUZU_NON_COPYABLE(ProxySocket);
YUZU_NON_MOVEABLE(ProxySocket);
explicit ProxySocket(RoomNetwork& room_network_) noexcept;
~ProxySocket() override;

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@ -36,13 +36,10 @@ public:
SocketBase() = default;
explicit SocketBase(SOCKET fd_) : fd{fd_} {}
virtual ~SocketBase() = default;
virtual SocketBase& operator=(const SocketBase&) = delete;
// Avoid closing sockets implicitly
virtual SocketBase& operator=(SocketBase&&) noexcept = delete;
YUZU_NON_COPYABLE(SocketBase);
YUZU_NON_MOVEABLE(SocketBase);
virtual Errno Initialize(Domain domain, Type type, Protocol protocol) = 0;
@ -109,14 +106,8 @@ public:
~Socket() override;
Socket(const Socket&) = delete;
Socket& operator=(const Socket&) = delete;
Socket(Socket&& rhs) noexcept;
// Avoid closing sockets implicitly
Socket& operator=(Socket&&) noexcept = delete;
Errno Initialize(Domain domain, Type type, Protocol protocol) override;
Errno Close() override;

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@ -152,7 +152,8 @@ std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::stri
return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture);
case TextureType::ColorArray2D:
case TextureType::ColorCube:
return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords, texture);
return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords,
texture);
default:
return std::string{coords};
}

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@ -266,30 +266,21 @@ Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info,
Id coords) {
// Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
// AMD hardware as on Maxwell or other Nvidia architectures.
const auto calculate_offset{[&](size_t dim) -> std::array<Id, 2> {
const auto calculate_coords{[&](size_t dim) {
const Id nudge{ctx.Const(0x1p-9f)};
const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)};
const Id offset_x{ctx.OpFDiv(
ctx.F32[1], nudge,
ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 0)))};
const Id offset_y{ctx.OpFDiv(
ctx.F32[1], nudge,
ctx.OpConvertUToF(ctx.F32[1], ctx.OpCompositeExtract(ctx.U32[1], image_size, 1)))};
return {ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 0), offset_x),
ctx.OpFAdd(ctx.F32[1], ctx.OpCompositeExtract(ctx.F32[1], coords, 1), offset_y)};
Id offset{dim == 2 ? ctx.ConstantComposite(ctx.F32[dim], nudge, nudge)
: ctx.ConstantComposite(ctx.F32[dim], nudge, nudge, ctx.f32_zero_value)};
offset = ctx.OpFDiv(ctx.F32[dim], offset, ctx.OpConvertUToF(ctx.F32[dim], image_size));
return ctx.OpFAdd(ctx.F32[dim], coords, offset);
}};
switch (info.type) {
case TextureType::Color2D:
case TextureType::Color2DRect: {
const auto offset{calculate_offset(2)};
return ctx.OpCompositeConstruct(ctx.F32[2], offset[0], offset[1]);
}
case TextureType::Color2DRect:
return calculate_coords(2);
case TextureType::ColorArray2D:
case TextureType::ColorCube: {
const auto offset{calculate_offset(3)};
return ctx.OpCompositeConstruct(ctx.F32[3], offset[0], offset[1],
ctx.OpCompositeExtract(ctx.F32[1], coords, 2));
}
case TextureType::ColorCube:
return calculate_coords(3);
default:
return coords;
}

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@ -52,9 +52,9 @@ struct Profile {
bool need_declared_frag_colors{};
/// Prevents fast math optimizations that may cause inaccuracies
bool need_fastmath_off{};
/// Some GPU vendors use a lower fixed point format of 16.8 when calculating pixel coordinates
/// in the ImageGather instruction than the Maxwell architecture does. Applying an offset does
/// fix this mismatching rounding behaviour.
/// Some GPU vendors use a different rounding precision when calculating texture pixel
/// coordinates with the 16.8 format in the ImageGather instruction than the Maxwell
/// architecture. Applying an offset does fix this mismatching rounding behaviour.
bool need_gather_subpixel_offset{};
/// OpFClamp is broken and OpFMax + OpFMin should be used instead

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@ -169,7 +169,6 @@ Device::Device(Core::Frontend::EmuWindow& emu_window) {
has_draw_texture = GLAD_GL_NV_draw_texture;
warp_size_potentially_larger_than_guest = !is_nvidia && !is_intel;
need_fastmath_off = is_nvidia;
need_gather_subpixel_offset = is_amd;
can_report_memory = GLAD_GL_NVX_gpu_memory_info;
// At the moment of writing this, only Nvidia's driver optimizes BufferSubData on exclusive

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@ -160,10 +160,6 @@ public:
return need_fastmath_off;
}
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
bool HasCbufFtouBug() const {
return has_cbuf_ftou_bug;
}
@ -180,6 +176,10 @@ public:
return vendor_name == "ATI Technologies Inc.";
}
bool IsIntel() const {
return vendor_name == "Intel";
}
bool CanReportMemoryUsage() const {
return can_report_memory;
}
@ -229,7 +229,6 @@ private:
bool has_draw_texture{};
bool warp_size_potentially_larger_than_guest{};
bool need_fastmath_off{};
bool need_gather_subpixel_offset{};
bool has_cbuf_ftou_bug{};
bool has_bool_ref_bug{};
bool can_report_memory{};

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@ -218,7 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
.lower_left_origin_mode = true,
.need_declared_frag_colors = true,
.need_fastmath_off = device.NeedsFastmathOff(),
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.need_gather_subpixel_offset = device.IsAmd() || device.IsIntel(),
.has_broken_spirv_clamp = true,
.has_broken_unsigned_image_offsets = true,

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@ -329,7 +329,9 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
.lower_left_origin_mode = false,
.need_declared_frag_colors = false,
.need_gather_subpixel_offset = device.NeedsGatherSubpixelOffset(),
.need_gather_subpixel_offset = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY ||
driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS ||
driver_id == VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA,
.has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
.has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,

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@ -431,7 +431,6 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
"AMD GCN4 and earlier have broken VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT");
has_broken_cube_compatibility = true;
}
need_gather_subpixel_offset = true;
}
if (extensions.sampler_filter_minmax && is_amd) {
// Disable ext_sampler_filter_minmax on AMD GCN4 and lower as it is broken.

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@ -554,10 +554,6 @@ public:
return features.robustness2.nullDescriptor;
}
bool NeedsGatherSubpixelOffset() const {
return need_gather_subpixel_offset;
}
u32 GetMaxVertexInputAttributes() const {
return properties.properties.limits.maxVertexInputAttributes;
}
@ -668,7 +664,6 @@ private:
bool must_emulate_bgr565{}; ///< Emulates BGR565 by swizzling RGB565 format.
bool dynamic_state3_blending{}; ///< Has all blending features of dynamic_state3.
bool dynamic_state3_enables{}; ///< Has all enables features of dynamic_state3.
bool need_gather_subpixel_offset{}; ///< Needs offset at ImageGather for correct rounding.
u64 device_access_memory{}; ///< Total size of device local memory in bytes.
u32 sets_per_pool{}; ///< Sets per Description Pool

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@ -21,7 +21,7 @@ bool VerifyLogin(const std::string& host, const std::string& username, const std
return username.empty();
}
return username == *iter;
return *iter == username;
}
} // namespace WebService