early-access version 3497
This commit is contained in:
parent
e16291336e
commit
53406e5574
@ -1,7 +1,7 @@
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yuzu emulator early access
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yuzu emulator early access
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=============
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=============
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This is the source code for early-access 3493.
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This is the source code for early-access 3497.
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## Legal Notice
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## Legal Notice
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@ -5,7 +5,6 @@
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#include <memory>
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#include <memory>
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#include <dynarmic/interface/A32/a32.h>
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#include <dynarmic/interface/A32/a32.h>
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#include <dynarmic/interface/A32/config.h>
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#include <dynarmic/interface/A32/config.h>
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#include <dynarmic/interface/A32/context.h>
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/literals.h"
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#include "common/literals.h"
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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@ -410,21 +409,19 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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}
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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Dynarmic::A32::Jit* j = jit.load();
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jit.load()->SaveContext(context);
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ctx.cpu_registers = j->Regs();
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ctx.cpu_registers = context.Regs();
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ctx.extension_registers = j->ExtRegs();
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ctx.extension_registers = context.ExtRegs();
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ctx.cpsr = j->Cpsr();
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ctx.cpsr = context.Cpsr();
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ctx.fpscr = j->Fpscr();
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ctx.fpscr = context.Fpscr();
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}
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}
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void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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Dynarmic::A32::Jit* j = jit.load();
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context.Regs() = ctx.cpu_registers;
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j->Regs() = ctx.cpu_registers;
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context.ExtRegs() = ctx.extension_registers;
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j->ExtRegs() = ctx.extension_registers;
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context.SetCpsr(ctx.cpsr);
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j->SetCpsr(ctx.cpsr);
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context.SetFpscr(ctx.fpscr);
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j->SetFpscr(ctx.fpscr);
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jit.load()->LoadContext(context);
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}
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}
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void ARM_Dynarmic_32::SignalInterrupt() {
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void ARM_Dynarmic_32::SignalInterrupt() {
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@ -70,7 +70,6 @@ Result Controller_NPad::VerifyValidSixAxisSensorHandle(
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const Core::HID::SixAxisSensorHandle& device_handle) {
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const Core::HID::SixAxisSensorHandle& device_handle) {
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const auto npad_id = IsNpadIdValid(static_cast<Core::HID::NpadIdType>(device_handle.npad_id));
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const auto npad_id = IsNpadIdValid(static_cast<Core::HID::NpadIdType>(device_handle.npad_id));
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const bool device_index = device_handle.device_index < Core::HID::DeviceIndex::MaxDeviceIndex;
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const bool device_index = device_handle.device_index < Core::HID::DeviceIndex::MaxDeviceIndex;
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const bool npad_type = device_handle.npad_type < Core::HID::NpadStyleIndex::MaxNpadType;
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if (!npad_id) {
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if (!npad_id) {
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return InvalidNpadId;
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return InvalidNpadId;
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@ -78,10 +77,6 @@ Result Controller_NPad::VerifyValidSixAxisSensorHandle(
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if (!device_index) {
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if (!device_index) {
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return NpadDeviceIndexOutOfRange;
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return NpadDeviceIndexOutOfRange;
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}
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}
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// This doesn't get validated on nnsdk
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if (!npad_type) {
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return NpadInvalidHandle;
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}
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return ResultSuccess;
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return ResultSuccess;
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}
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}
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@ -1131,6 +1126,7 @@ Result Controller_NPad::DisconnectNpad(Core::HID::NpadIdType npad_id) {
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WriteEmptyEntry(shared_memory);
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WriteEmptyEntry(shared_memory);
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return ResultSuccess;
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return ResultSuccess;
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}
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}
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Result Controller_NPad::SetGyroscopeZeroDriftMode(
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Result Controller_NPad::SetGyroscopeZeroDriftMode(
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const Core::HID::SixAxisSensorHandle& sixaxis_handle,
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const Core::HID::SixAxisSensorHandle& sixaxis_handle,
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Core::HID::GyroscopeZeroDriftMode drift_mode) {
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Core::HID::GyroscopeZeroDriftMode drift_mode) {
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@ -856,8 +856,8 @@ public:
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struct ZetaSize {
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struct ZetaSize {
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enum class DimensionControl : u32 {
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enum class DimensionControl : u32 {
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DepthDefinesArray = 0,
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DefineArraySize = 0,
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ArraySizeOne = 1,
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ArraySizeIsOne = 1,
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};
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};
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u32 width;
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u32 width;
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@ -1104,8 +1104,8 @@ public:
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struct TileMode {
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struct TileMode {
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enum class DimensionControl : u32 {
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enum class DimensionControl : u32 {
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DepthDefinesArray = 0,
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DefineArraySize = 0,
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DepthDefinesDepth = 1,
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DefineDepthSize = 1,
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};
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};
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union {
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union {
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BitField<0, 4, u32> block_width;
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BitField<0, 4, u32> block_width;
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namespace VideoCommon {
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namespace VideoCommon {
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using Tegra::Engines::Fermi2D;
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using Tegra::Engines::Maxwell3D;
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using Tegra::Engines::Maxwell3D;
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using Tegra::Texture::TextureType;
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using Tegra::Texture::TextureType;
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using Tegra::Texture::TICEntry;
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using Tegra::Texture::TICEntry;
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@ -114,86 +115,89 @@ ImageInfo::ImageInfo(const TICEntry& config) noexcept {
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}
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}
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}
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}
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ImageInfo::ImageInfo(const Maxwell3D::Regs& regs, size_t index) noexcept {
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ImageInfo::ImageInfo(const Maxwell3D::Regs::RenderTargetConfig& ct,
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const auto& rt = regs.rt[index];
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Tegra::Texture::MsaaMode msaa_mode) noexcept {
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(rt.format);
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(ct.format);
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rescaleable = false;
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rescaleable = false;
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if (rt.tile_mode.is_pitch_linear) {
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if (ct.tile_mode.is_pitch_linear) {
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ASSERT(rt.tile_mode.dim_control ==
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ASSERT(ct.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
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Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
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type = ImageType::Linear;
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type = ImageType::Linear;
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pitch = rt.width;
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pitch = ct.width;
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size = Extent3D{
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size = Extent3D{
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.width = pitch / BytesPerBlock(format),
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.width = pitch / BytesPerBlock(format),
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.height = rt.height,
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.height = ct.height,
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.depth = 1,
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.depth = 1,
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};
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};
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return;
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return;
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}
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}
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size.width = rt.width;
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size.width = ct.width;
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size.height = rt.height;
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size.height = ct.height;
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layer_stride = rt.array_pitch * 4;
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layer_stride = ct.array_pitch * 4;
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maybe_unaligned_layer_stride = layer_stride;
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maybe_unaligned_layer_stride = layer_stride;
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num_samples = NumSamples(regs.anti_alias_samples_mode);
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num_samples = NumSamples(msaa_mode);
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block = Extent3D{
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block = Extent3D{
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.width = rt.tile_mode.block_width,
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.width = ct.tile_mode.block_width,
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.height = rt.tile_mode.block_height,
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.height = ct.tile_mode.block_height,
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.depth = rt.tile_mode.block_depth,
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.depth = ct.tile_mode.block_depth,
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};
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};
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if (rt.tile_mode.dim_control ==
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if (ct.tile_mode.dim_control == Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
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type = ImageType::e3D;
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type = ImageType::e3D;
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size.depth = rt.depth;
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size.depth = ct.depth;
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} else {
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} else {
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rescaleable = block.depth == 0;
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rescaleable = block.depth == 0;
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rescaleable &= size.height > 256;
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rescaleable &= size.height > 256;
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downscaleable = size.height > 512;
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downscaleable = size.height > 512;
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type = ImageType::e2D;
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type = ImageType::e2D;
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resources.layers = rt.depth;
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resources.layers = ct.depth;
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}
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}
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}
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}
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ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs) noexcept {
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ImageInfo::ImageInfo(const Maxwell3D::Regs::Zeta& zt, const Maxwell3D::Regs::ZetaSize& zt_size,
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format = VideoCore::Surface::PixelFormatFromDepthFormat(regs.zeta.format);
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Tegra::Texture::MsaaMode msaa_mode) noexcept {
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size.width = regs.zeta_size.width;
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format = VideoCore::Surface::PixelFormatFromDepthFormat(zt.format);
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size.height = regs.zeta_size.height;
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size.width = zt_size.width;
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size.height = zt_size.height;
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rescaleable = false;
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rescaleable = false;
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resources.levels = 1;
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resources.levels = 1;
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layer_stride = regs.zeta.array_pitch * 4;
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layer_stride = zt.array_pitch * 4;
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maybe_unaligned_layer_stride = layer_stride;
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maybe_unaligned_layer_stride = layer_stride;
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num_samples = NumSamples(regs.anti_alias_samples_mode);
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num_samples = NumSamples(msaa_mode);
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block = Extent3D{
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block = Extent3D{
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.width = regs.zeta.tile_mode.block_width,
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.width = zt.tile_mode.block_width,
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.height = regs.zeta.tile_mode.block_height,
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.height = zt.tile_mode.block_height,
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.depth = regs.zeta.tile_mode.block_depth,
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.depth = zt.tile_mode.block_depth,
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};
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};
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if (regs.zeta.tile_mode.is_pitch_linear) {
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if (zt.tile_mode.is_pitch_linear) {
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ASSERT(regs.zeta.tile_mode.dim_control ==
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ASSERT(zt.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
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Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
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type = ImageType::Linear;
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type = ImageType::Linear;
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pitch = size.width * BytesPerBlock(format);
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pitch = size.width * BytesPerBlock(format);
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} else if (regs.zeta.tile_mode.dim_control ==
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} else if (zt.tile_mode.dim_control ==
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Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
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Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
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ASSERT(regs.zeta.tile_mode.is_pitch_linear == 0);
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ASSERT(zt_size.dim_control == Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne);
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ASSERT(regs.zeta_size.dim_control ==
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Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeOne);
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type = ImageType::e3D;
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type = ImageType::e3D;
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size.depth = regs.zeta_size.depth;
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size.depth = zt_size.depth;
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} else {
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} else {
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ASSERT(regs.zeta_size.dim_control ==
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Maxwell3D::Regs::ZetaSize::DimensionControl::DepthDefinesArray);
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rescaleable = block.depth == 0;
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rescaleable = block.depth == 0;
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downscaleable = size.height > 512;
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downscaleable = size.height > 512;
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type = ImageType::e2D;
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type = ImageType::e2D;
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resources.layers = regs.zeta_size.depth;
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switch (zt_size.dim_control) {
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case Maxwell3D::Regs::ZetaSize::DimensionControl::DefineArraySize:
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resources.layers = zt_size.depth;
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break;
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case Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne:
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resources.layers = 1;
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break;
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}
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}
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}
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}
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}
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ImageInfo::ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept {
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ImageInfo::ImageInfo(const Fermi2D::Surface& config) noexcept {
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UNIMPLEMENTED_IF_MSG(config.layer != 0, "Surface layer is not zero");
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UNIMPLEMENTED_IF_MSG(config.layer != 0, "Surface layer is not zero");
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(config.format);
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format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(config.format);
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rescaleable = false;
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rescaleable = false;
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if (config.linear == Tegra::Engines::Fermi2D::MemoryLayout::Pitch) {
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if (config.linear == Fermi2D::MemoryLayout::Pitch) {
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type = ImageType::Linear;
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type = ImageType::Linear;
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size = Extent3D{
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size = Extent3D{
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.width = config.pitch / VideoCore::Surface::BytesPerBlock(format),
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.width = config.pitch / VideoCore::Surface::BytesPerBlock(format),
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struct ImageInfo {
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struct ImageInfo {
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ImageInfo() = default;
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ImageInfo() = default;
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explicit ImageInfo(const TICEntry& config) noexcept;
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explicit ImageInfo(const TICEntry& config) noexcept;
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explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs, size_t index) noexcept;
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explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& ct,
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explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs) noexcept;
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Tegra::Texture::MsaaMode msaa_mode) noexcept;
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explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs::Zeta& zt,
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const Tegra::Engines::Maxwell3D::Regs::ZetaSize& zt_size,
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Tegra::Texture::MsaaMode msaa_mode) noexcept;
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explicit ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept;
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explicit ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept;
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explicit ImageInfo(const Tegra::DMA::ImageOperand& config) noexcept;
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explicit ImageInfo(const Tegra::DMA::ImageOperand& config) noexcept;
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@ -1503,7 +1503,7 @@ ImageViewId TextureCache<P>::FindColorBuffer(size_t index, bool is_clear) {
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if (rt.format == Tegra::RenderTargetFormat::NONE) {
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if (rt.format == Tegra::RenderTargetFormat::NONE) {
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return ImageViewId{};
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return ImageViewId{};
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}
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}
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const ImageInfo info(regs, index);
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const ImageInfo info(regs.rt[index], regs.anti_alias_samples_mode);
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return FindRenderTargetView(info, gpu_addr, is_clear);
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return FindRenderTargetView(info, gpu_addr, is_clear);
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}
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}
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@ -1517,7 +1517,7 @@ ImageViewId TextureCache<P>::FindDepthBuffer(bool is_clear) {
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if (gpu_addr == 0) {
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if (gpu_addr == 0) {
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return ImageViewId{};
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return ImageViewId{};
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}
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}
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const ImageInfo info(regs);
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const ImageInfo info(regs.zeta, regs.zeta_size, regs.anti_alias_samples_mode);
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return FindRenderTargetView(info, gpu_addr, is_clear);
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return FindRenderTargetView(info, gpu_addr, is_clear);
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}
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}
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