hdkv/yuzu
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early-access version 2148

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pineappleEA 2021-10-19 19:46:36 +02:00
parent e4df473e46
commit 6a02e7140f
4 changed files with 26 additions and 7 deletions
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2
README.md
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@ -1,7 +1,7 @@
yuzu emulator early access yuzu emulator early access
============= =============
This is the source code for early-access 2147. This is the source code for early-access 2148.
## Legal Notice ## Legal Notice

21
src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
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@ -355,11 +355,22 @@ Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value&
Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
Id coords, Id dref, Id bias_lc, const IR::Value& offset) { Id coords, Id dref, Id bias_lc, const IR::Value& offset) {
const auto info{inst->Flags<IR::TextureInstInfo>()}; const auto info{inst->Flags<IR::TextureInstInfo>()};
const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, bias_lc, if (ctx.stage == Stage::Fragment) {
offset); const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0,
return Emit(&EmitContext::OpImageSparseSampleDrefImplicitLod, bias_lc, offset);
&EmitContext::OpImageSampleDrefImplicitLod, ctx, inst, ctx.F32[1], return Emit(&EmitContext::OpImageSparseSampleDrefImplicitLod,
Texture(ctx, info, index), coords, dref, operands.MaskOptional(), operands.Span()); &EmitContext::OpImageSampleDrefImplicitLod, ctx, inst, ctx.F32[1],
Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
operands.Span());
} else {
// Implicit lods in compute behave on hardware as if sampling from LOD 0.
// This check is to ensure all drivers behave this way.
const Id lod{ctx.Const(0.0f)};
const ImageOperands operands(ctx, false, true, false, lod, offset);
return Emit(&EmitContext::OpImageSparseSampleDrefExplicitLod,
&EmitContext::OpImageSampleDrefExplicitLod, ctx, inst, ctx.F32[1],
Texture(ctx, info, index), coords, dref, operands.Mask(), operands.Span());
}
} }
Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,

3
src/video_core/renderer_vulkan/vk_rasterizer.cpp
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@ -592,7 +592,8 @@ void RasterizerVulkan::EndTransformFeedback() {
} }
void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D::Regs& regs) { void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D::Regs& regs) {
if (!state_tracker.TouchViewports()) { if (!state_tracker.TouchViewports() &&
!state_tracker.ChangedYNegate(regs.screen_y_control.y_negate)) {
return; return;
} }
const std::array viewports{ const std::array viewports{

7
src/video_core/renderer_vulkan/vk_state_tracker.h
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@ -137,6 +137,12 @@ public:
return has_changed; return has_changed;
} }
bool ChangedYNegate(u32 new_y_negate) {
const bool has_changed = current_y_negate != new_y_negate;
current_y_negate = new_y_negate;
return has_changed;
}
private: private:
static constexpr auto INVALID_TOPOLOGY = static_cast<Maxwell::PrimitiveTopology>(~0u); static constexpr auto INVALID_TOPOLOGY = static_cast<Maxwell::PrimitiveTopology>(~0u);
@ -149,6 +155,7 @@ private:
Tegra::Engines::Maxwell3D::DirtyState::Flags& flags; Tegra::Engines::Maxwell3D::DirtyState::Flags& flags;
Tegra::Engines::Maxwell3D::DirtyState::Flags invalidation_flags; Tegra::Engines::Maxwell3D::DirtyState::Flags invalidation_flags;
Maxwell::PrimitiveTopology current_topology = INVALID_TOPOLOGY; Maxwell::PrimitiveTopology current_topology = INVALID_TOPOLOGY;
u32 current_y_negate{};
}; };
} // namespace Vulkan } // namespace Vulkan