early-access version 1255
This commit is contained in:
pineappleEA
374
externals/dynarmic/tests/A32/fuzz_arm.cpp
vendored
Executable file
374
externals/dynarmic/tests/A32/fuzz_arm.cpp
vendored
Executable file
@@ -0,0 +1,374 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
#include <cstdio>
|
||||
#include <functional>
|
||||
#include <tuple>
|
||||
#include <vector>
|
||||
|
||||
#include <catch.hpp>
|
||||
#include <dynarmic/A32/a32.h>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "common/fp/fpcr.h"
|
||||
#include "common/fp/fpsr.h"
|
||||
#include "common/scope_exit.h"
|
||||
#include "frontend/A32/disassembler/disassembler.h"
|
||||
#include "frontend/A32/location_descriptor.h"
|
||||
#include "frontend/A32/translate/translate.h"
|
||||
#include "frontend/A32/types.h"
|
||||
#include "frontend/ir/basic_block.h"
|
||||
#include "frontend/ir/location_descriptor.h"
|
||||
#include "frontend/ir/opcodes.h"
|
||||
#include "fuzz_util.h"
|
||||
#include "rand_int.h"
|
||||
#include "testenv.h"
|
||||
#include "unicorn_emu/a32_unicorn.h"
|
||||
|
||||
// Must be declared last for all necessary operator<< to be declared prior to this.
|
||||
#include <fmt/format.h>
|
||||
#include <fmt/ostream.h>
|
||||
|
||||
namespace {
|
||||
using namespace Dynarmic;
|
||||
|
||||
bool ShouldTestInst(u32 instruction, u32 pc, bool is_last_inst) {
|
||||
const A32::LocationDescriptor location{pc, {}, {}};
|
||||
IR::Block block{location};
|
||||
const bool should_continue = A32::TranslateSingleInstruction(block, location, instruction);
|
||||
|
||||
if (!should_continue && !is_last_inst) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (auto terminal = block.GetTerminal(); boost::get<IR::Term::Interpret>(&terminal)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
for (const auto& ir_inst : block) {
|
||||
switch (ir_inst.GetOpcode()) {
|
||||
case IR::Opcode::A32ExceptionRaised:
|
||||
case IR::Opcode::A32CallSupervisor:
|
||||
case IR::Opcode::A32CoprocInternalOperation:
|
||||
case IR::Opcode::A32CoprocSendOneWord:
|
||||
case IR::Opcode::A32CoprocSendTwoWords:
|
||||
case IR::Opcode::A32CoprocGetOneWord:
|
||||
case IR::Opcode::A32CoprocGetTwoWords:
|
||||
case IR::Opcode::A32CoprocLoadWords:
|
||||
case IR::Opcode::A32CoprocStoreWords:
|
||||
return false;
|
||||
// Currently unimplemented in Unicorn
|
||||
case IR::Opcode::FPVectorRecipEstimate16:
|
||||
case IR::Opcode::FPVectorRSqrtEstimate16:
|
||||
case IR::Opcode::VectorPolynomialMultiplyLong64:
|
||||
return false;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u32 GenRandomInst(u32 pc, bool is_last_inst) {
|
||||
static const struct InstructionGeneratorInfo {
|
||||
std::vector<InstructionGenerator> generators;
|
||||
std::vector<InstructionGenerator> invalid;
|
||||
} instructions = []{
|
||||
const std::vector<std::tuple<std::string, const char*>> list {
|
||||
#define INST(fn, name, bitstring) {#fn, bitstring},
|
||||
#include "frontend/A32/decoder/arm.inc"
|
||||
#include "frontend/A32/decoder/asimd.inc"
|
||||
#include "frontend/A32/decoder/vfp.inc"
|
||||
#undef INST
|
||||
};
|
||||
|
||||
std::vector<InstructionGenerator> generators;
|
||||
std::vector<InstructionGenerator> invalid;
|
||||
|
||||
// List of instructions not to test
|
||||
static constexpr std::array do_not_test {
|
||||
// Translating load/stores
|
||||
"arm_LDRBT", "arm_LDRBT", "arm_LDRHT", "arm_LDRHT", "arm_LDRSBT", "arm_LDRSBT", "arm_LDRSHT", "arm_LDRSHT", "arm_LDRT", "arm_LDRT",
|
||||
"arm_STRBT", "arm_STRBT", "arm_STRHT", "arm_STRHT", "arm_STRT", "arm_STRT",
|
||||
// Exclusive load/stores
|
||||
"arm_LDREXB", "arm_LDREXD", "arm_LDREXH", "arm_LDREX", "arm_LDAEXB", "arm_LDAEXD", "arm_LDAEXH", "arm_LDAEX",
|
||||
"arm_STREXB", "arm_STREXD", "arm_STREXH", "arm_STREX", "arm_STLEXB", "arm_STLEXD", "arm_STLEXH", "arm_STLEX",
|
||||
"arm_SWP", "arm_SWPB",
|
||||
// Elevated load/store multiple instructions.
|
||||
"arm_LDM_eret", "arm_LDM_usr",
|
||||
"arm_STM_usr",
|
||||
// Hint instructions
|
||||
"arm_NOP", "arm_PLD_imm", "arm_PLD_reg", "arm_SEV",
|
||||
"arm_WFE", "arm_WFI", "arm_YIELD",
|
||||
// E, T, J
|
||||
"arm_BLX_reg", "arm_BLX_imm", "arm_BXJ", "arm_SETEND",
|
||||
// Coprocessor
|
||||
"arm_CDP", "arm_LDC", "arm_MCR", "arm_MCRR", "arm_MRC", "arm_MRRC", "arm_STC",
|
||||
// System
|
||||
"arm_CPS", "arm_RFE", "arm_SRS",
|
||||
// Undefined
|
||||
"arm_UDF",
|
||||
// FPSCR is inaccurate
|
||||
"vfp_VMRS",
|
||||
// Incorrect Unicorn implementations
|
||||
"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
|
||||
"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
|
||||
"vfp_VCVT_from_fixed", // Unicorn does not do round-to-nearest-even for this instruction correctly.
|
||||
};
|
||||
|
||||
for (const auto& [fn, bitstring] : list) {
|
||||
if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
|
||||
invalid.emplace_back(InstructionGenerator{bitstring});
|
||||
continue;
|
||||
}
|
||||
generators.emplace_back(InstructionGenerator{bitstring});
|
||||
}
|
||||
return InstructionGeneratorInfo{generators, invalid};
|
||||
}();
|
||||
|
||||
while (true) {
|
||||
const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
|
||||
const u32 inst = instructions.generators[index].Generate();
|
||||
|
||||
if ((instructions.generators[index].Mask() & 0xF0000000) == 0 && (inst & 0xF0000000) == 0xF0000000) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (ShouldTestInst(inst, pc, is_last_inst)) {
|
||||
return inst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Dynarmic::A32::UserConfig GetUserConfig(ArmTestEnv& testenv) {
|
||||
Dynarmic::A32::UserConfig user_config;
|
||||
user_config.optimizations &= ~OptimizationFlag::FastDispatch;
|
||||
user_config.callbacks = &testenv;
|
||||
user_config.always_little_endian = true;
|
||||
return user_config;
|
||||
}
|
||||
|
||||
static void RunTestInstance(Dynarmic::A32::Jit& jit, A32Unicorn<ArmTestEnv>& uni,
|
||||
ArmTestEnv& jit_env, ArmTestEnv& uni_env,
|
||||
const A32Unicorn<ArmTestEnv>::RegisterArray& regs,
|
||||
const A32Unicorn<ArmTestEnv>::ExtRegArray& vecs,
|
||||
const std::vector<u32>& instructions, const u32 cpsr, const u32 fpscr) {
|
||||
const u32 initial_pc = regs[15];
|
||||
const u32 num_words = initial_pc / sizeof(u32);
|
||||
const u32 code_mem_size = num_words + static_cast<u32>(instructions.size());
|
||||
|
||||
jit_env.code_mem.resize(code_mem_size + 1);
|
||||
uni_env.code_mem.resize(code_mem_size + 1);
|
||||
|
||||
std::copy(instructions.begin(), instructions.end(), jit_env.code_mem.begin() + num_words);
|
||||
std::copy(instructions.begin(), instructions.end(), uni_env.code_mem.begin() + num_words);
|
||||
jit_env.code_mem.back() = 0xEAFFFFFE; // B .
|
||||
uni_env.code_mem.back() = 0xEAFFFFFE; // B .
|
||||
jit_env.modified_memory.clear();
|
||||
uni_env.modified_memory.clear();
|
||||
jit_env.interrupts.clear();
|
||||
uni_env.interrupts.clear();
|
||||
|
||||
jit.Regs() = regs;
|
||||
jit.ExtRegs() = vecs;
|
||||
jit.SetFpscr(fpscr);
|
||||
jit.SetCpsr(cpsr);
|
||||
jit.ClearCache();
|
||||
uni.SetRegisters(regs);
|
||||
uni.SetExtRegs(vecs);
|
||||
uni.SetFpscr(fpscr);
|
||||
uni.EnableFloatingPointAccess();
|
||||
uni.SetCpsr(cpsr);
|
||||
uni.ClearPageCache();
|
||||
|
||||
jit_env.ticks_left = instructions.size();
|
||||
jit.Run();
|
||||
|
||||
uni_env.ticks_left = instructions.size();
|
||||
uni.Run();
|
||||
|
||||
SCOPE_FAIL {
|
||||
fmt::print("Instruction Listing:\n");
|
||||
for (u32 instruction : instructions) {
|
||||
fmt::print("{:08x} {}\n", instruction, A32::DisassembleArm(instruction));
|
||||
}
|
||||
fmt::print("\n");
|
||||
|
||||
fmt::print("Initial register listing:\n");
|
||||
for (size_t i = 0; i < regs.size(); ++i) {
|
||||
fmt::print("{:3s}: {:08x}\n", static_cast<A32::Reg>(i), regs[i]);
|
||||
}
|
||||
for (size_t i = 0; i < vecs.size(); ++i) {
|
||||
fmt::print("{:3s}: {:08x}\n", static_cast<A32::ExtReg>(i), vecs[i]);
|
||||
}
|
||||
fmt::print("cpsr {:08x}\n", cpsr);
|
||||
fmt::print("fpcr {:08x}\n", fpscr);
|
||||
fmt::print("fpcr.AHP {}\n", FP::FPCR{fpscr}.AHP());
|
||||
fmt::print("fpcr.DN {}\n", FP::FPCR{fpscr}.DN());
|
||||
fmt::print("fpcr.FZ {}\n", FP::FPCR{fpscr}.FZ());
|
||||
fmt::print("fpcr.RMode {}\n", static_cast<size_t>(FP::FPCR{fpscr}.RMode()));
|
||||
fmt::print("fpcr.FZ16 {}\n", FP::FPCR{fpscr}.FZ16());
|
||||
fmt::print("\n");
|
||||
|
||||
fmt::print("Final register listing:\n");
|
||||
fmt::print(" unicorn dynarmic\n");
|
||||
const auto uni_regs = uni.GetRegisters();
|
||||
for (size_t i = 0; i < regs.size(); ++i) {
|
||||
fmt::print("{:3s}: {:08x} {:08x} {}\n", static_cast<A32::Reg>(i), uni_regs[i], jit.Regs()[i], uni_regs[i] != jit.Regs()[i] ? "*" : "");
|
||||
}
|
||||
const auto uni_ext_regs = uni.GetExtRegs();
|
||||
for (size_t i = 0; i < vecs.size(); ++i) {
|
||||
fmt::print("s{:2d}: {:08x} {:08x} {}\n", static_cast<size_t>(i), uni_ext_regs[i], jit.ExtRegs()[i], uni_ext_regs[i] != jit.ExtRegs()[i] ? "*" : "");
|
||||
}
|
||||
fmt::print("cpsr {:08x} {:08x} {}\n", uni.GetCpsr(), jit.Cpsr(), uni.GetCpsr() != jit.Cpsr() ? "*" : "");
|
||||
fmt::print("fpsr {:08x} {:08x} {}\n", uni.GetFpscr(), jit.Fpscr(), (uni.GetFpscr() & 0xF0000000) != (jit.Fpscr() & 0xF0000000) ? "*" : "");
|
||||
fmt::print("\n");
|
||||
|
||||
fmt::print("Modified memory:\n");
|
||||
fmt::print(" uni dyn\n");
|
||||
auto uni_iter = uni_env.modified_memory.begin();
|
||||
auto jit_iter = jit_env.modified_memory.begin();
|
||||
while (uni_iter != uni_env.modified_memory.end() || jit_iter != jit_env.modified_memory.end()) {
|
||||
if (uni_iter == uni_env.modified_memory.end() || (jit_iter != jit_env.modified_memory.end() && uni_iter->first > jit_iter->first)) {
|
||||
fmt::print("{:08x}: {:02x} *\n", jit_iter->first, jit_iter->second);
|
||||
jit_iter++;
|
||||
} else if (jit_iter == jit_env.modified_memory.end() || jit_iter->first > uni_iter->first) {
|
||||
fmt::print("{:08x}: {:02x} *\n", uni_iter->first, uni_iter->second);
|
||||
uni_iter++;
|
||||
} else if (uni_iter->first == jit_iter->first) {
|
||||
fmt::print("{:08x}: {:02x} {:02x} {}\n", uni_iter->first, uni_iter->second, jit_iter->second, uni_iter->second != jit_iter->second ? "*" : "");
|
||||
uni_iter++;
|
||||
jit_iter++;
|
||||
}
|
||||
}
|
||||
fmt::print("\n");
|
||||
|
||||
fmt::print("x86_64:\n");
|
||||
fmt::print("{}\n", jit.Disassemble());
|
||||
|
||||
fmt::print("Interrupts:\n");
|
||||
for (const auto& i : uni_env.interrupts) {
|
||||
std::puts(i.c_str());
|
||||
}
|
||||
};
|
||||
|
||||
REQUIRE(uni_env.code_mem_modified_by_guest == jit_env.code_mem_modified_by_guest);
|
||||
if (uni_env.code_mem_modified_by_guest) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Qemu doesn't do Thumb transitions??
|
||||
{
|
||||
const u32 uni_pc = uni.GetPC();
|
||||
const bool is_thumb = (jit.Cpsr() & (1 << 5)) != 0;
|
||||
const u32 new_uni_pc = uni_pc & (is_thumb ? 0xFFFFFFFE : 0xFFFFFFFC);
|
||||
uni.SetPC(new_uni_pc);
|
||||
}
|
||||
|
||||
REQUIRE(uni.GetRegisters() == jit.Regs());
|
||||
REQUIRE(uni.GetExtRegs() == jit.ExtRegs());
|
||||
REQUIRE((uni.GetCpsr() & 0xFFFFFDDF) == (jit.Cpsr() & 0xFFFFFDDF));
|
||||
REQUIRE((uni.GetFpscr() & 0xF0000000) == (jit.Fpscr() & 0xF0000000));
|
||||
REQUIRE(uni_env.modified_memory == jit_env.modified_memory);
|
||||
REQUIRE(uni_env.interrupts.empty());
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
TEST_CASE("A32: Single random instruction", "[arm]") {
|
||||
ArmTestEnv jit_env{};
|
||||
ArmTestEnv uni_env{};
|
||||
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
||||
A32Unicorn<ArmTestEnv> uni{uni_env};
|
||||
|
||||
A32Unicorn<ArmTestEnv>::RegisterArray regs;
|
||||
A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
|
||||
std::vector<u32> instructions(1);
|
||||
|
||||
for (size_t iteration = 0; iteration < 100000; ++iteration) {
|
||||
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
|
||||
instructions[0] = GenRandomInst(0, true);
|
||||
|
||||
const u32 start_address = 100;
|
||||
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
|
||||
const u32 fpcr = RandomFpcr();
|
||||
|
||||
INFO("Instruction: 0x" << std::hex << instructions[0]);
|
||||
|
||||
regs[15] = start_address;
|
||||
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("A32: Small random block", "[arm]") {
|
||||
ArmTestEnv jit_env{};
|
||||
ArmTestEnv uni_env{};
|
||||
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
||||
A32Unicorn<ArmTestEnv> uni{uni_env};
|
||||
|
||||
A32Unicorn<ArmTestEnv>::RegisterArray regs;
|
||||
A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
|
||||
std::vector<u32> instructions(5);
|
||||
|
||||
for (size_t iteration = 0; iteration < 100000; ++iteration) {
|
||||
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
|
||||
instructions[0] = GenRandomInst(0, false);
|
||||
instructions[1] = GenRandomInst(4, false);
|
||||
instructions[2] = GenRandomInst(8, false);
|
||||
instructions[3] = GenRandomInst(12, false);
|
||||
instructions[4] = GenRandomInst(16, true);
|
||||
|
||||
const u32 start_address = 100;
|
||||
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
|
||||
const u32 fpcr = RandomFpcr();
|
||||
|
||||
INFO("Instruction 1: 0x" << std::hex << instructions[0]);
|
||||
INFO("Instruction 2: 0x" << std::hex << instructions[1]);
|
||||
INFO("Instruction 3: 0x" << std::hex << instructions[2]);
|
||||
INFO("Instruction 4: 0x" << std::hex << instructions[3]);
|
||||
INFO("Instruction 5: 0x" << std::hex << instructions[4]);
|
||||
|
||||
regs[15] = start_address;
|
||||
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("A32: Large random block", "[arm]") {
|
||||
ArmTestEnv jit_env{};
|
||||
ArmTestEnv uni_env{};
|
||||
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(jit_env)};
|
||||
A32Unicorn<ArmTestEnv> uni{uni_env};
|
||||
|
||||
A32Unicorn<ArmTestEnv>::RegisterArray regs;
|
||||
A32Unicorn<ArmTestEnv>::ExtRegArray ext_reg;
|
||||
|
||||
constexpr size_t instruction_count = 100;
|
||||
std::vector<u32> instructions(instruction_count);
|
||||
|
||||
for (size_t iteration = 0; iteration < 10000; ++iteration) {
|
||||
std::generate(regs.begin(), regs.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
std::generate(ext_reg.begin(), ext_reg.end(), [] { return RandInt<u32>(0, ~u32(0)); });
|
||||
|
||||
for (size_t j = 0; j < instruction_count; ++j) {
|
||||
instructions[j] = GenRandomInst(j * 4, j == instruction_count - 1);
|
||||
}
|
||||
|
||||
const u64 start_address = 100;
|
||||
const u32 cpsr = (RandInt<u32>(0, 0xF) << 28) | 0x10;
|
||||
const u32 fpcr = RandomFpcr();
|
||||
|
||||
regs[15] = start_address;
|
||||
RunTestInstance(jit, uni, jit_env, uni_env, regs, ext_reg, instructions, cpsr, fpcr);
|
||||
}
|
||||
}
|
||||
351
externals/dynarmic/tests/A32/fuzz_thumb.cpp
vendored
Executable file
351
externals/dynarmic/tests/A32/fuzz_thumb.cpp
vendored
Executable file
@@ -0,0 +1,351 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
#include <cinttypes>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <functional>
|
||||
#include <tuple>
|
||||
|
||||
#include <catch.hpp>
|
||||
|
||||
#include <dynarmic/A32/a32.h>
|
||||
|
||||
#include "common/bit_util.h"
|
||||
#include "common/common_types.h"
|
||||
#include "frontend/A32/disassembler/disassembler.h"
|
||||
#include "frontend/A32/FPSCR.h"
|
||||
#include "frontend/A32/location_descriptor.h"
|
||||
#include "frontend/A32/PSR.h"
|
||||
#include "frontend/A32/translate/translate.h"
|
||||
#include "frontend/ir/basic_block.h"
|
||||
#include "ir_opt/passes.h"
|
||||
#include "rand_int.h"
|
||||
#include "testenv.h"
|
||||
#include "unicorn_emu/a32_unicorn.h"
|
||||
|
||||
using namespace Dynarmic;
|
||||
|
||||
static A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
|
||||
A32::UserConfig user_config;
|
||||
user_config.optimizations &= ~OptimizationFlag::FastDispatch;
|
||||
user_config.callbacks = testenv;
|
||||
return user_config;
|
||||
}
|
||||
|
||||
using WriteRecords = std::map<u32, u8>;
|
||||
|
||||
struct ThumbInstGen final {
|
||||
public:
|
||||
ThumbInstGen(const char* format, std::function<bool(u16)> is_valid = [](u16){ return true; }) : is_valid(is_valid) {
|
||||
REQUIRE(strlen(format) == 16);
|
||||
|
||||
for (int i = 0; i < 16; i++) {
|
||||
const u16 bit = 1 << (15 - i);
|
||||
switch (format[i]) {
|
||||
case '0':
|
||||
mask |= bit;
|
||||
break;
|
||||
case '1':
|
||||
bits |= bit;
|
||||
mask |= bit;
|
||||
break;
|
||||
default:
|
||||
// Do nothing
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
u16 Generate() const {
|
||||
u16 inst;
|
||||
|
||||
do {
|
||||
const u16 random = RandInt<u16>(0, 0xFFFF);
|
||||
inst = bits | (random & ~mask);
|
||||
} while (!is_valid(inst));
|
||||
|
||||
ASSERT((inst & mask) == bits);
|
||||
|
||||
return inst;
|
||||
}
|
||||
private:
|
||||
u16 bits = 0;
|
||||
u16 mask = 0;
|
||||
std::function<bool(u16)> is_valid;
|
||||
};
|
||||
|
||||
static bool DoesBehaviorMatch(const A32Unicorn<ThumbTestEnv>& uni, const A32::Jit& jit,
|
||||
const WriteRecords& interp_write_records, const WriteRecords& jit_write_records) {
|
||||
const auto interp_regs = uni.GetRegisters();
|
||||
const auto jit_regs = jit.Regs();
|
||||
|
||||
return std::equal(interp_regs.begin(), interp_regs.end(), jit_regs.begin(), jit_regs.end()) &&
|
||||
uni.GetCpsr() == jit.Cpsr() &&
|
||||
interp_write_records == jit_write_records;
|
||||
}
|
||||
|
||||
static void RunInstance(size_t run_number, ThumbTestEnv& test_env, A32Unicorn<ThumbTestEnv>& uni, A32::Jit& jit, const ThumbTestEnv::RegisterArray& initial_regs,
|
||||
size_t instruction_count, size_t instructions_to_execute_count) {
|
||||
uni.ClearPageCache();
|
||||
jit.ClearCache();
|
||||
|
||||
// Setup initial state
|
||||
|
||||
uni.SetCpsr(0x000001F0);
|
||||
uni.SetRegisters(initial_regs);
|
||||
jit.SetCpsr(0x000001F0);
|
||||
jit.Regs() = initial_regs;
|
||||
|
||||
// Run interpreter
|
||||
test_env.modified_memory.clear();
|
||||
test_env.ticks_left = instructions_to_execute_count;
|
||||
uni.SetPC(uni.GetPC() | 1);
|
||||
uni.Run();
|
||||
const bool uni_code_memory_modified = test_env.code_mem_modified_by_guest;
|
||||
const auto interp_write_records = test_env.modified_memory;
|
||||
|
||||
// Run jit
|
||||
test_env.code_mem_modified_by_guest = false;
|
||||
test_env.modified_memory.clear();
|
||||
test_env.ticks_left = instructions_to_execute_count;
|
||||
jit.Run();
|
||||
const bool jit_code_memory_modified = test_env.code_mem_modified_by_guest;
|
||||
const auto jit_write_records = test_env.modified_memory;
|
||||
test_env.code_mem_modified_by_guest = false;
|
||||
|
||||
REQUIRE(uni_code_memory_modified == jit_code_memory_modified);
|
||||
if (uni_code_memory_modified) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Compare
|
||||
if (!DoesBehaviorMatch(uni, jit, interp_write_records, jit_write_records)) {
|
||||
printf("Failed at execution number %zu\n", run_number);
|
||||
|
||||
printf("\nInstruction Listing: \n");
|
||||
for (size_t i = 0; i < instruction_count; i++) {
|
||||
printf("%04x %s\n", test_env.code_mem[i], A32::DisassembleThumb16(test_env.code_mem[i]).c_str());
|
||||
}
|
||||
|
||||
printf("\nInitial Register Listing: \n");
|
||||
for (size_t i = 0; i < initial_regs.size(); i++) {
|
||||
printf("%4zu: %08x\n", i, initial_regs[i]);
|
||||
}
|
||||
|
||||
printf("\nFinal Register Listing: \n");
|
||||
printf(" unicorn jit\n");
|
||||
const auto uni_registers = uni.GetRegisters();
|
||||
for (size_t i = 0; i < uni_registers.size(); i++) {
|
||||
printf("%4zu: %08x %08x %s\n", i, uni_registers[i], jit.Regs()[i], uni_registers[i] != jit.Regs()[i] ? "*" : "");
|
||||
}
|
||||
printf("CPSR: %08x %08x %s\n", uni.GetCpsr(), jit.Cpsr(), uni.GetCpsr() != jit.Cpsr() ? "*" : "");
|
||||
|
||||
printf("\nUnicorn Write Records:\n");
|
||||
for (const auto& record : interp_write_records) {
|
||||
printf("[%08x] = %02x\n", record.first, record.second);
|
||||
}
|
||||
|
||||
printf("\nJIT Write Records:\n");
|
||||
for (const auto& record : jit_write_records) {
|
||||
printf("[%08x] = %02x\n", record.first, record.second);
|
||||
}
|
||||
|
||||
A32::PSR cpsr;
|
||||
cpsr.T(true);
|
||||
|
||||
size_t num_insts = 0;
|
||||
while (num_insts < instructions_to_execute_count) {
|
||||
A32::LocationDescriptor descriptor = {u32(num_insts * 4), cpsr, A32::FPSCR{}};
|
||||
IR::Block ir_block = A32::Translate(descriptor, [&test_env](u32 vaddr) { return test_env.MemoryReadCode(vaddr); }, {});
|
||||
Optimization::A32GetSetElimination(ir_block);
|
||||
Optimization::DeadCodeElimination(ir_block);
|
||||
Optimization::A32ConstantMemoryReads(ir_block, &test_env);
|
||||
Optimization::ConstantPropagation(ir_block);
|
||||
Optimization::DeadCodeElimination(ir_block);
|
||||
Optimization::VerificationPass(ir_block);
|
||||
printf("\n\nIR:\n%s", IR::DumpBlock(ir_block).c_str());
|
||||
printf("\n\nx86_64:\n%s", jit.Disassemble().c_str());
|
||||
num_insts += ir_block.CycleCount();
|
||||
}
|
||||
|
||||
#ifdef _MSC_VER
|
||||
__debugbreak();
|
||||
#endif
|
||||
FAIL();
|
||||
}
|
||||
}
|
||||
|
||||
void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_execute_count, const size_t run_count, const std::function<u16()> instruction_generator) {
|
||||
ThumbTestEnv test_env;
|
||||
|
||||
// Prepare memory.
|
||||
test_env.code_mem.resize(instruction_count + 1);
|
||||
test_env.code_mem.back() = 0xE7FE; // b +#0
|
||||
|
||||
// Prepare test subjects
|
||||
A32Unicorn uni{test_env};
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
|
||||
for (size_t run_number = 0; run_number < run_count; run_number++) {
|
||||
ThumbTestEnv::RegisterArray initial_regs;
|
||||
std::generate_n(initial_regs.begin(), initial_regs.size() - 1, []{ return RandInt<u32>(0, 0xFFFFFFFF); });
|
||||
initial_regs[15] = 0;
|
||||
|
||||
std::generate_n(test_env.code_mem.begin(), instruction_count, instruction_generator);
|
||||
|
||||
RunInstance(run_number, test_env, uni, jit, initial_regs, instruction_count, instructions_to_execute_count);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") {
|
||||
const std::array instructions = {
|
||||
ThumbInstGen("00000xxxxxxxxxxx"), // LSL <Rd>, <Rm>, #<imm5>
|
||||
ThumbInstGen("00001xxxxxxxxxxx"), // LSR <Rd>, <Rm>, #<imm5>
|
||||
ThumbInstGen("00010xxxxxxxxxxx"), // ASR <Rd>, <Rm>, #<imm5>
|
||||
ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg
|
||||
ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm
|
||||
ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm
|
||||
ThumbInstGen("010000ooooxxxxxx"), // Data Processing
|
||||
ThumbInstGen("010001000hxxxxxx"), // ADD (high registers)
|
||||
ThumbInstGen("0100010101xxxxxx", // CMP (high registers)
|
||||
[](u16 inst){ return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE
|
||||
ThumbInstGen("0100010110xxxxxx", // CMP (high registers)
|
||||
[](u16 inst){ return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE
|
||||
ThumbInstGen("010001100hxxxxxx"), // MOV (high registers)
|
||||
ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer
|
||||
ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT
|
||||
ThumbInstGen("1011101000xxxxxx"), // REV
|
||||
ThumbInstGen("1011101001xxxxxx"), // REV16
|
||||
ThumbInstGen("1011101011xxxxxx"), // REVSH
|
||||
ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #]
|
||||
ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm]
|
||||
ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #]
|
||||
ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset]
|
||||
ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #]
|
||||
ThumbInstGen("1011010xxxxxxxxx", // PUSH
|
||||
[](u16 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
|
||||
ThumbInstGen("10111100xxxxxxxx", // POP (P = 0)
|
||||
[](u16 inst){ return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE
|
||||
ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA
|
||||
[](u16 inst) {
|
||||
// Ensure that the architecturally undefined case of
|
||||
// the base register being within the list isn't hit.
|
||||
const u32 rn = Common::Bits<8, 10>(inst);
|
||||
return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0;
|
||||
}),
|
||||
// TODO: We should properly test against swapped
|
||||
// endianness cases, however Unicorn doesn't
|
||||
// expose the intended endianness of a load/store
|
||||
// operation to memory through its hooks.
|
||||
#if 0
|
||||
ThumbInstGen("101101100101x000"), // SETEND
|
||||
#endif
|
||||
};
|
||||
|
||||
const auto instruction_select = [&]() -> u16 {
|
||||
size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
|
||||
|
||||
return instructions[inst_index].Generate();
|
||||
};
|
||||
|
||||
SECTION("single instructions") {
|
||||
FuzzJitThumb(1, 2, 10000, instruction_select);
|
||||
}
|
||||
|
||||
SECTION("short blocks") {
|
||||
FuzzJitThumb(5, 6, 3000, instruction_select);
|
||||
}
|
||||
|
||||
// TODO: Test longer blocks when Unicorn can consistently
|
||||
// run these without going into an infinite loop.
|
||||
#if 0
|
||||
SECTION("long blocks") {
|
||||
FuzzJitThumb(1024, 1025, 1000, instruction_select);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb]") {
|
||||
const std::array instructions = {
|
||||
// TODO: We currently can't test BX/BLX as we have
|
||||
// no way of preventing the unpredictable
|
||||
// condition from occurring with the current interface.
|
||||
// (bits zero and one within the specified register
|
||||
// must not be address<1:0> == '10'.
|
||||
#if 0
|
||||
ThumbInstGen("01000111xmmmm000", // BLX/BX
|
||||
[](u16 inst){
|
||||
const u32 Rm = Common::Bits<3, 6>(inst);
|
||||
return Rm != 15;
|
||||
}),
|
||||
#endif
|
||||
ThumbInstGen("1010oxxxxxxxxxxx"), // add to pc/sp
|
||||
ThumbInstGen("11100xxxxxxxxxxx"), // B
|
||||
ThumbInstGen("01000100h0xxxxxx"), // ADD (high registers)
|
||||
ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers)
|
||||
ThumbInstGen("1101ccccxxxxxxxx", // B<cond>
|
||||
[](u16 inst){
|
||||
const u32 c = Common::Bits<9, 12>(inst);
|
||||
return c < 0b1110; // Don't want SWI or undefined instructions.
|
||||
}),
|
||||
ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ
|
||||
ThumbInstGen("10110110011x0xxx"), // CPS
|
||||
|
||||
// TODO: We currently have no control over the generated
|
||||
// values when creating new pages, so we can't
|
||||
// reliably test this yet.
|
||||
#if 0
|
||||
ThumbInstGen("10111101xxxxxxxx"), // POP (R = 1)
|
||||
#endif
|
||||
};
|
||||
|
||||
const auto instruction_select = [&]() -> u16 {
|
||||
size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
|
||||
|
||||
return instructions[inst_index].Generate();
|
||||
};
|
||||
|
||||
FuzzJitThumb(1, 1, 10000, instruction_select);
|
||||
}
|
||||
|
||||
TEST_CASE("Verify fix for off by one error in MemoryRead32 worked", "[Thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
|
||||
// Prepare test subjects
|
||||
A32Unicorn<ThumbTestEnv> uni{test_env};
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
|
||||
constexpr ThumbTestEnv::RegisterArray initial_regs {
|
||||
0xe90ecd70,
|
||||
0x3e3b73c3,
|
||||
0x571616f9,
|
||||
0x0b1ef45a,
|
||||
0xb3a829f2,
|
||||
0x915a7a6a,
|
||||
0x579c38f4,
|
||||
0xd9ffe391,
|
||||
0x55b6682b,
|
||||
0x458d8f37,
|
||||
0x8f3eb3dc,
|
||||
0xe18c0e7d,
|
||||
0x6752657a,
|
||||
0x00001766,
|
||||
0xdbbf23e3,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
test_env.code_mem = {
|
||||
0x40B8, // lsls r0, r7, #0
|
||||
0x01CA, // lsls r2, r1, #7
|
||||
0x83A1, // strh r1, [r4, #28]
|
||||
0x708A, // strb r2, [r1, #2]
|
||||
0xBCC4, // pop {r2, r6, r7}
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
RunInstance(1, test_env, uni, jit, initial_regs, 5, 5);
|
||||
}
|
||||
381
externals/dynarmic/tests/A32/test_arm_disassembler.cpp
vendored
Executable file
381
externals/dynarmic/tests/A32/test_arm_disassembler.cpp
vendored
Executable file
@@ -0,0 +1,381 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#include <catch.hpp>
|
||||
|
||||
#include "frontend/A32/disassembler/disassembler.h"
|
||||
|
||||
using Dynarmic::A32::DisassembleArm;
|
||||
|
||||
TEST_CASE("Disassemble branch instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xEAFFFFFE) == "b +#0");
|
||||
REQUIRE(DisassembleArm(0xEB000008) == "bl +#40");
|
||||
REQUIRE(DisassembleArm(0xFBFFFFFE) == "blx +#2");
|
||||
REQUIRE(DisassembleArm(0xFAFFFFFF) == "blx +#4");
|
||||
REQUIRE(DisassembleArm(0xFBE1E7FE) == "blx -#7888894");
|
||||
REQUIRE(DisassembleArm(0xE12FFF3D) == "blx sp");
|
||||
REQUIRE(DisassembleArm(0x312FFF13) == "bxcc r3");
|
||||
REQUIRE(DisassembleArm(0x012FFF29) == "bxjeq r9");
|
||||
}
|
||||
|
||||
TEST_CASE("Disassemble data processing instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xE2A21004) == "adc r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0A21143) == "adc r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0A21103) == "adc r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0A21123) == "adc r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0A21163) == "adc r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0A21003) == "adc r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0A21063) == "adc r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0A21453) == "adc r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0A21413) == "adc r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0A21433) == "adc r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0A21473) == "adc r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE2B21004) == "adcs r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0B21143) == "adcs r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0B21103) == "adcs r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0B21123) == "adcs r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0B21163) == "adcs r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0B21003) == "adcs r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0B21063) == "adcs r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0B21453) == "adcs r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0B21413) == "adcs r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0B21433) == "adcs r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0B21473) == "adcs r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2853004) == "add r3, r5, #4");
|
||||
REQUIRE(DisassembleArm(0xE0821143) == "add r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0821103) == "add r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0821123) == "add r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0821163) == "add r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0821003) == "add r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0821453) == "add r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0821413) == "add r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0821433) == "add r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0821473) == "add r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE0821063) == "add r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE2953004) == "adds r3, r5, #4");
|
||||
REQUIRE(DisassembleArm(0xE0921143) == "adds r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0921103) == "adds r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0921123) == "adds r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0921163) == "adds r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0921003) == "adds r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0921063) == "adds r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0921453) == "adds r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0921413) == "adds r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0921433) == "adds r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0921473) == "adds r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2021004) == "and r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0021143) == "and r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0021103) == "and r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0021123) == "and r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0021163) == "and r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0021003) == "and r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0021453) == "and r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0021413) == "and r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0021433) == "and r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0021473) == "and r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE0021063) == "and r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE2121004) == "ands r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0121143) == "ands r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0121103) == "ands r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0121123) == "ands r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0121163) == "ands r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0121003) == "ands r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0121063) == "ands r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0121453) == "ands r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0121413) == "ands r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0121433) == "ands r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0121473) == "ands r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3C21004) == "bic r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE1C21143) == "bic r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1C21103) == "bic r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1C21123) == "bic r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1C21163) == "bic r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1C21003) == "bic r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE1C21453) == "bic r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE1C21413) == "bic r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE1C21433) == "bic r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE1C21473) == "bic r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE1C21063) == "bic r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE3D21004) == "bics r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE1D21143) == "bics r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1D21103) == "bics r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1D21123) == "bics r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1D21163) == "bics r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1D21003) == "bics r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE1D21063) == "bics r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1D21453) == "bics r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE1D21413) == "bics r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE1D21433) == "bics r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE1D21473) == "bics r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3710004) == "cmn r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1710142) == "cmn r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1710102) == "cmn r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1710122) == "cmn r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1710162) == "cmn r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1710002) == "cmn r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1710062) == "cmn r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1710352) == "cmn r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1710312) == "cmn r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1710332) == "cmn r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1710372) == "cmn r1, r2, ror r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3510004) == "cmp r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1510142) == "cmp r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1510102) == "cmp r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1510122) == "cmp r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1510162) == "cmp r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1510002) == "cmp r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1510062) == "cmp r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1510352) == "cmp r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1510312) == "cmp r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1510332) == "cmp r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1510372) == "cmp r1, r2, ror r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2221004) == "eor r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0221243) == "eor r1, r2, r3, asr #4");
|
||||
REQUIRE(DisassembleArm(0xE0221203) == "eor r1, r2, r3, lsl #4");
|
||||
REQUIRE(DisassembleArm(0xE0221223) == "eor r1, r2, r3, lsr #4");
|
||||
REQUIRE(DisassembleArm(0xE0221263) == "eor r1, r2, r3, ror #4");
|
||||
REQUIRE(DisassembleArm(0xE0221003) == "eor r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0221453) == "eor r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0221413) == "eor r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0221433) == "eor r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0221473) == "eor r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE0221063) == "eor r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE2321004) == "eors r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0321243) == "eors r1, r2, r3, asr #4");
|
||||
REQUIRE(DisassembleArm(0xE0321203) == "eors r1, r2, r3, lsl #4");
|
||||
REQUIRE(DisassembleArm(0xE0321223) == "eors r1, r2, r3, lsr #4");
|
||||
REQUIRE(DisassembleArm(0xE0321263) == "eors r1, r2, r3, ror #4");
|
||||
REQUIRE(DisassembleArm(0xE0321003) == "eors r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0321453) == "eors r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0321413) == "eors r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0321433) == "eors r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0321473) == "eors r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE0321063) == "eors r1, r2, r3, rrx");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3A010FF) == "mov r1, #255");
|
||||
REQUIRE(DisassembleArm(0xE1A01142) == "mov r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1A01102) == "mov r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1A01122) == "mov r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1A01162) == "mov r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1A01062) == "mov r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1A0E00F) == "mov lr, pc");
|
||||
REQUIRE(DisassembleArm(0xE3B010FF) == "movs r1, #255");
|
||||
REQUIRE(DisassembleArm(0xE1B0E00F) == "movs lr, pc");
|
||||
REQUIRE(DisassembleArm(0xE1B01142) == "movs r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1B01102) == "movs r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1B01122) == "movs r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1B01162) == "movs r1, r2, ror #2");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3E01004) == "mvn r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1E01142) == "mvn r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1E01102) == "mvn r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1E01122) == "mvn r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1E01162) == "mvn r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1E01062) == "mvn r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1E01002) == "mvn r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1E01352) == "mvn r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1E01312) == "mvn r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1E01332) == "mvn r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1E01372) == "mvn r1, r2, ror r3");
|
||||
REQUIRE(DisassembleArm(0xE3F01004) == "mvns r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1F01142) == "mvns r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1F01102) == "mvns r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1F01122) == "mvns r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1F01162) == "mvns r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1F01062) == "mvns r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1F01002) == "mvns r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1F01352) == "mvns r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1F01312) == "mvns r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1F01332) == "mvns r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1F01372) == "mvns r1, r2, ror r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3821004) == "orr r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE1821143) == "orr r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1821103) == "orr r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1821123) == "orr r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1821163) == "orr r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1821063) == "orr r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1821003) == "orr r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE1821453) == "orr r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE1821413) == "orr r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE1821433) == "orr r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE1821473) == "orr r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE3921004) == "orrs r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE1921143) == "orrs r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1921103) == "orrs r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1921123) == "orrs r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1921163) == "orrs r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1921063) == "orrs r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1921003) == "orrs r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE1921453) == "orrs r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE1921413) == "orrs r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE1921433) == "orrs r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE1921473) == "orrs r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2621004) == "rsb r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0621143) == "rsb r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0621103) == "rsb r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0621123) == "rsb r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0621163) == "rsb r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0621063) == "rsb r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0621003) == "rsb r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0621453) == "rsb r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0621413) == "rsb r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0621433) == "rsb r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0621473) == "rsb r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE2721004) == "rsbs r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0721143) == "rsbs r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0721103) == "rsbs r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0721123) == "rsbs r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0721163) == "rsbs r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0721063) == "rsbs r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0721003) == "rsbs r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0721453) == "rsbs r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0721413) == "rsbs r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0721433) == "rsbs r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0721473) == "rsbs r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2E21004) == "rsc r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0E21143) == "rsc r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0E21103) == "rsc r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0E21123) == "rsc r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0E21163) == "rsc r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0E21063) == "rsc r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0E21003) == "rsc r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0E21453) == "rsc r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0E21413) == "rsc r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0E21433) == "rsc r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0E21473) == "rsc r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE2F21004) == "rscs r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0F21143) == "rscs r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0F21103) == "rscs r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0F21123) == "rscs r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0F21163) == "rscs r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0F21063) == "rscs r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0F21003) == "rscs r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0F21453) == "rscs r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0F21413) == "rscs r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0F21433) == "rscs r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0F21473) == "rscs r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE2C21004) == "sbc r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0C21143) == "sbc r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0C21103) == "sbc r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0C21123) == "sbc r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0C21163) == "sbc r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0C21063) == "sbc r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0C21003) == "sbc r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0C21453) == "sbc r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0C21413) == "sbc r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0C21433) == "sbc r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0C21473) == "sbc r1, r2, r3, ror r4");
|
||||
REQUIRE(DisassembleArm(0xE2D21004) == "sbcs r1, r2, #4");
|
||||
REQUIRE(DisassembleArm(0xE0D21143) == "sbcs r1, r2, r3, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE0D21103) == "sbcs r1, r2, r3, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE0D21123) == "sbcs r1, r2, r3, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE0D21163) == "sbcs r1, r2, r3, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE0D21063) == "sbcs r1, r2, r3, rrx");
|
||||
REQUIRE(DisassembleArm(0xE0D21003) == "sbcs r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0D21453) == "sbcs r1, r2, r3, asr r4");
|
||||
REQUIRE(DisassembleArm(0xE0D21413) == "sbcs r1, r2, r3, lsl r4");
|
||||
REQUIRE(DisassembleArm(0xE0D21433) == "sbcs r1, r2, r3, lsr r4");
|
||||
REQUIRE(DisassembleArm(0xE0D21473) == "sbcs r1, r2, r3, ror r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3310004) == "teq r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1310142) == "teq r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1310102) == "teq r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1310122) == "teq r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1310162) == "teq r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1310002) == "teq r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1310062) == "teq r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1310352) == "teq r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1310312) == "teq r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1310332) == "teq r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1310372) == "teq r1, r2, ror r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE3110004) == "tst r1, #4");
|
||||
REQUIRE(DisassembleArm(0xE1110142) == "tst r1, r2, asr #2");
|
||||
REQUIRE(DisassembleArm(0xE1110102) == "tst r1, r2, lsl #2");
|
||||
REQUIRE(DisassembleArm(0xE1110122) == "tst r1, r2, lsr #2");
|
||||
REQUIRE(DisassembleArm(0xE1110162) == "tst r1, r2, ror #2");
|
||||
REQUIRE(DisassembleArm(0xE1110002) == "tst r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE1110062) == "tst r1, r2, rrx");
|
||||
REQUIRE(DisassembleArm(0xE1110352) == "tst r1, r2, asr r3");
|
||||
REQUIRE(DisassembleArm(0xE1110312) == "tst r1, r2, lsl r3");
|
||||
REQUIRE(DisassembleArm(0xE1110332) == "tst r1, r2, lsr r3");
|
||||
REQUIRE(DisassembleArm(0xE1110372) == "tst r1, r2, ror r3");
|
||||
}
|
||||
|
||||
TEST_CASE("Disassemble half-word multiply and multiply accumulate instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xE1003281) == "smlabb r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE10032C1) == "smlabt r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE10032A1) == "smlatb r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE10032E1) == "smlatt r0, r1, r2, r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE1203281) == "smlawb r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE12032C1) == "smlawt r0, r1, r2, r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE12002A1) == "smulwb r0, r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE12002E1) == "smulwt r0, r1, r2");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE1410382) == "smlalbb r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE14103C2) == "smlalbt r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE14103A2) == "smlaltb r0, r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE14103E2) == "smlaltt r0, r1, r2, r3");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE1600281) == "smulbb r0, r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE16002C1) == "smulbt r0, r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE16002A1) == "smultb r0, r1, r2");
|
||||
REQUIRE(DisassembleArm(0xE16002E1) == "smultt r0, r1, r2");
|
||||
}
|
||||
|
||||
TEST_CASE("Disassemble multiply and multiply accumulate instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xE0214392) == "mla r1, r2, r3, r4");
|
||||
REQUIRE(DisassembleArm(0xE0314392) == "mlas r1, r2, r3, r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0010392) == "mul r1, r2, r3");
|
||||
REQUIRE(DisassembleArm(0xE0110392) == "muls r1, r2, r3");
|
||||
|
||||
// TODO: MLS should be here whenever it's supported.
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0E21493) == "smlal r1, r2, r3, r4");
|
||||
REQUIRE(DisassembleArm(0xE0F21493) == "smlals r1, r2, r3, r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0C21493) == "smull r1, r2, r3, r4");
|
||||
REQUIRE(DisassembleArm(0xE0D21493) == "smulls r1, r2, r3, r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0421493) == "umaal r1, r2, r3, r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0A21493) == "umlal r1, r2, r3, r4");
|
||||
REQUIRE(DisassembleArm(0xE0B21493) == "umlals r1, r2, r3, r4");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE0821493) == "umull r1, r2, r3, r4");
|
||||
REQUIRE(DisassembleArm(0xE0921493) == "umulls r1, r2, r3, r4");
|
||||
}
|
||||
|
||||
TEST_CASE("Disassemble synchronization primitive instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xE1921F9F) == "ldrex r1, [r2]");
|
||||
REQUIRE(DisassembleArm(0xE1D21F9F) == "ldrexb r1, [r2]");
|
||||
REQUIRE(DisassembleArm(0xE1B31F9F) == "ldrexd r1, r2, [r3]");
|
||||
REQUIRE(DisassembleArm(0xE1F21F9F) == "ldrexh r1, [r2]");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE1831F92) == "strex r1, r2, [r3]");
|
||||
REQUIRE(DisassembleArm(0xE1C31F92) == "strexb r1, r2, [r3]");
|
||||
REQUIRE(DisassembleArm(0xE1A41F92) == "strexd r1, r2, r3, [r4]");
|
||||
REQUIRE(DisassembleArm(0xE1E31F92) == "strexh r1, r2, [r3]");
|
||||
|
||||
REQUIRE(DisassembleArm(0xE1031092) == "swp r1, r2, [r3]");
|
||||
REQUIRE(DisassembleArm(0xE1431092) == "swpb r1, r2, [r3]");
|
||||
}
|
||||
|
||||
TEST_CASE("Disassemble load / store multiple instructions", "[arm][disassembler]") {
|
||||
REQUIRE(DisassembleArm(0xE92D500F) == "stmdb sp!, {r0, r1, r2, r3, r12, lr}");
|
||||
}
|
||||
507
externals/dynarmic/tests/A32/test_arm_instructions.cpp
vendored
Executable file
507
externals/dynarmic/tests/A32/test_arm_instructions.cpp
vendored
Executable file
@@ -0,0 +1,507 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#include <catch.hpp>
|
||||
#include <dynarmic/A32/a32.h>
|
||||
|
||||
#include "A32/testenv.h"
|
||||
#include "frontend/A32/location_descriptor.h"
|
||||
|
||||
using namespace Dynarmic;
|
||||
|
||||
static A32::UserConfig GetUserConfig(ArmTestEnv* testenv) {
|
||||
A32::UserConfig user_config;
|
||||
user_config.optimizations &= ~OptimizationFlag::FastDispatch;
|
||||
user_config.callbacks = testenv;
|
||||
return user_config;
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Opt Failure: Const folding in MostSignificantWord", "[arm][A32]") {
|
||||
// This was a randomized test-case that was failing.
|
||||
// This was due to constant folding for MostSignificantWord
|
||||
// failing to take into account an associated GetCarryFromOp
|
||||
// pseudoinstruction.
|
||||
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe30ad071, // movw, sp, #41073
|
||||
0xe75efd3d, // smmulr lr, sp, sp
|
||||
0xa637af1e, // shadd16ge r10, r7, lr
|
||||
0xf57ff01f, // clrex
|
||||
0x86b98879, // sxtahhi r8, r9, r9, ror #16
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 6;
|
||||
jit.Run();
|
||||
|
||||
// If we don't trigger the GetCarryFromOp ASSERT, we're fine.
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Unintended modification in SetCFlag", "[arm][A32]") {
|
||||
// This was a randomized test-case that was failing.
|
||||
//
|
||||
// IR produced for location {12, !T, !E} was:
|
||||
// %0 = GetRegister r1
|
||||
// %1 = SubWithCarry %0, #0x3e80000, #1
|
||||
// %2 = GetCarryFromOp %1
|
||||
// %3 = GetOverflowFromOp %1
|
||||
// %4 = MostSignificantBit %1
|
||||
// SetNFlag %4
|
||||
// %6 = IsZero %1
|
||||
// SetZFlag %6
|
||||
// SetCFlag %2
|
||||
// SetVFlag %3
|
||||
// %10 = GetRegister r5
|
||||
// %11 = AddWithCarry %10, #0x8a00, %2
|
||||
// SetRegister r4, %11
|
||||
//
|
||||
// The reference to %2 in instruction %11 was the issue, because instruction %8
|
||||
// told the register allocator it was a Use but then modified the value.
|
||||
// Changing the EmitSet*Flag instruction to declare their arguments as UseScratch
|
||||
// solved this bug.
|
||||
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe35f0cd9, // cmp pc, #55552
|
||||
0xe11c0474, // tst r12, r4, ror r4
|
||||
0xe1a006a7, // mov r0, r7, lsr #13
|
||||
0xe35107fa, // cmp r1, #0x3E80000
|
||||
0xe2a54c8a, // adc r4, r5, #35328
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs() = {
|
||||
0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5,
|
||||
0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0
|
||||
};
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 6;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 0x00000af1);
|
||||
REQUIRE(jit.Regs()[1] == 0x267ea626);
|
||||
REQUIRE(jit.Regs()[2] == 0x69debf49);
|
||||
REQUIRE(jit.Regs()[3] == 0x8f976895);
|
||||
REQUIRE(jit.Regs()[4] == 0xcf8a42c8);
|
||||
REQUIRE(jit.Regs()[5] == 0xcf89b8c7);
|
||||
REQUIRE(jit.Regs()[6] == 0xb6713f85);
|
||||
REQUIRE(jit.Regs()[7] == 0x015e2aa5);
|
||||
REQUIRE(jit.Regs()[8] == 0xcd14336a);
|
||||
REQUIRE(jit.Regs()[9] == 0xafca0f3e);
|
||||
REQUIRE(jit.Regs()[10] == 0xace2efd9);
|
||||
REQUIRE(jit.Regs()[11] == 0x68fb82cd);
|
||||
REQUIRE(jit.Regs()[12] == 0x775447c0);
|
||||
REQUIRE(jit.Regs()[13] == 0xc9e1f8cd);
|
||||
REQUIRE(jit.Regs()[14] == 0xebe0e626);
|
||||
REQUIRE(jit.Regs()[15] == 0x00000014);
|
||||
REQUIRE(jit.Cpsr() == 0x200001d0);
|
||||
}
|
||||
|
||||
TEST_CASE( "arm: shsax (Edge-case)", "[arm][A32]" ) {
|
||||
// This was a randomized test-case that was failing.
|
||||
//
|
||||
// The issue here was one of the words to be subtracted was 0x8000.
|
||||
// When the 2s complement was calculated by (~a + 1), it was 0x8000.
|
||||
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe63dbf59, // shsax r11, sp, r9
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs() = {
|
||||
0x3a3b8b18, 0x96156555, 0xffef039f, 0xafb946f2, 0x2030a69a, 0xafe09b2a, 0x896823c8, 0xabde0ded,
|
||||
0x9825d6a6, 0x17498000, 0x999d2c95, 0x8b812a59, 0x209bdb58, 0x2f7fb1d4, 0x0f378107, 0x00000000
|
||||
};
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 2;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 0x3a3b8b18);
|
||||
REQUIRE(jit.Regs()[1] == 0x96156555);
|
||||
REQUIRE(jit.Regs()[2] == 0xffef039f);
|
||||
REQUIRE(jit.Regs()[3] == 0xafb946f2);
|
||||
REQUIRE(jit.Regs()[4] == 0x2030a69a);
|
||||
REQUIRE(jit.Regs()[5] == 0xafe09b2a);
|
||||
REQUIRE(jit.Regs()[6] == 0x896823c8);
|
||||
REQUIRE(jit.Regs()[7] == 0xabde0ded);
|
||||
REQUIRE(jit.Regs()[8] == 0x9825d6a6);
|
||||
REQUIRE(jit.Regs()[9] == 0x17498000);
|
||||
REQUIRE(jit.Regs()[10] == 0x999d2c95);
|
||||
REQUIRE(jit.Regs()[11] == 0x57bfe48e);
|
||||
REQUIRE(jit.Regs()[12] == 0x209bdb58);
|
||||
REQUIRE(jit.Regs()[13] == 0x2f7fb1d4);
|
||||
REQUIRE(jit.Regs()[14] == 0x0f378107);
|
||||
REQUIRE(jit.Regs()[15] == 0x00000004);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE( "arm: uasx (Edge-case)", "[arm][A32]" ) {
|
||||
// UASX's Rm<31:16> == 0x0000.
|
||||
// An implementation that depends on addition overflow to detect
|
||||
// if diff >= 0 will fail this testcase.
|
||||
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe6549f35, // uasx r9, r4, r5
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[4] = 0x8ed38f4c;
|
||||
jit.Regs()[5] = 0x0000261d;
|
||||
jit.Regs()[15] = 0x00000000;
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 2;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[4] == 0x8ed38f4c);
|
||||
REQUIRE(jit.Regs()[5] == 0x0000261d);
|
||||
REQUIRE(jit.Regs()[9] == 0xb4f08f4c);
|
||||
REQUIRE(jit.Regs()[15] == 0x00000004);
|
||||
REQUIRE(jit.Cpsr() == 0x000301d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: smuad (Edge-case)", "[arm][A32]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xE700F211, // smuad r0, r1, r2
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs() = {
|
||||
0, // Rd
|
||||
0x80008000, // Rn
|
||||
0x80008000, // Rm
|
||||
0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
};
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 2;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 0x80000000);
|
||||
REQUIRE(jit.Regs()[1] == 0x80008000);
|
||||
REQUIRE(jit.Regs()[2] == 0x80008000);
|
||||
REQUIRE(jit.Cpsr() == 0x080001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Test InvalidateCacheRange", "[arm][A32]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe3a00005, // mov r0, #5
|
||||
0xe3a0100D, // mov r1, #13
|
||||
0xe0812000, // add r2, r1, r0
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs() = {};
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 4;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 5);
|
||||
REQUIRE(jit.Regs()[1] == 13);
|
||||
REQUIRE(jit.Regs()[2] == 18);
|
||||
REQUIRE(jit.Regs()[15] == 0x0000000c);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
|
||||
// Change the code
|
||||
test_env.code_mem[1] = 0xe3a01007; // mov r1, #7
|
||||
jit.InvalidateCacheRange(/*start_memory_location = */ 4, /* length_in_bytes = */ 4);
|
||||
|
||||
// Reset position of PC
|
||||
jit.Regs()[15] = 0;
|
||||
|
||||
test_env.ticks_left = 4;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 5);
|
||||
REQUIRE(jit.Regs()[1] == 7);
|
||||
REQUIRE(jit.Regs()[2] == 12);
|
||||
REQUIRE(jit.Regs()[15] == 0x0000000c);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Step blx", "[arm]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::UserConfig config = GetUserConfig(&test_env);
|
||||
config.optimizations |= OptimizationFlag::FastDispatch;
|
||||
Dynarmic::A32::Jit jit{config};
|
||||
test_env.code_mem = {
|
||||
0xe12fff30, // blx r0
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 8;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 10;
|
||||
jit.Step();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 8);
|
||||
REQUIRE(jit.Regs()[14] == 4);
|
||||
REQUIRE(jit.Regs()[15] == 8);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Step bx", "[arm]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::UserConfig config = GetUserConfig(&test_env);
|
||||
config.optimizations |= OptimizationFlag::FastDispatch;
|
||||
Dynarmic::A32::Jit jit{config};
|
||||
test_env.code_mem = {
|
||||
0xe12fff10, // bx r0
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 8;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 10;
|
||||
jit.Step();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 8);
|
||||
REQUIRE(jit.Regs()[15] == 8);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
|
||||
TEST_CASE("arm: Test stepping", "[arm]") {
|
||||
ArmTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 8;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
for (size_t i = 0; i < 5; ++i) {
|
||||
test_env.ticks_left = 10;
|
||||
jit.Step();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == (i + 1) * 4);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
test_env.ticks_left = 20;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == 80);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Test stepping 2", "[arm]") {
|
||||
ArmTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe12fff10, // bx r0
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 4;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
for (size_t i = 0; i < 5; ++i) {
|
||||
test_env.ticks_left = 10;
|
||||
jit.Step();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == (i + 1) * 4);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
test_env.ticks_left = 20;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == 80);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: Test stepping 3", "[arm]") {
|
||||
ArmTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xe12fff10, // bx r0
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
0xe320f000, // nop
|
||||
|
||||
0xeafffffe, // b +#0 (infinite loop)
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 4;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 10;
|
||||
jit.Step();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == 4);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
|
||||
test_env.ticks_left = 20;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[15] == 20);
|
||||
REQUIRE(jit.Cpsr() == 0x000001d0);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: PackedAbsDiffSumS8", "[arm][A32]") {
|
||||
// This was a randomized test-case that was failing.
|
||||
// In circumstances there were cases when the upper 32 bits of an argument to psadbw were not zero.
|
||||
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0x87414354, // smlsldhi r4, r1, r4, r3
|
||||
0xe7886412, // usad8a r8, r2, r4, r6
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs() = {
|
||||
0xea85297c, 0x417ad918, 0x64f8b70b, 0xcca0373e, 0xbc722361, 0xc528c69e, 0xca926de8, 0xd665d210,
|
||||
0xb5650555, 0x4a24b25b, 0xaed44144, 0xe87230b2, 0x98e391de, 0x126efc0c, 0xe591fd11, 0x00000000,
|
||||
};
|
||||
jit.SetCpsr(0xb0000010);
|
||||
|
||||
test_env.ticks_left = 3;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 0xea85297c);
|
||||
REQUIRE(jit.Regs()[1] == 0x417ad918);
|
||||
REQUIRE(jit.Regs()[2] == 0x64f8b70b);
|
||||
REQUIRE(jit.Regs()[3] == 0xcca0373e);
|
||||
REQUIRE(jit.Regs()[4] == 0xb685ec9f);
|
||||
REQUIRE(jit.Regs()[5] == 0xc528c69e);
|
||||
REQUIRE(jit.Regs()[6] == 0xca926de8);
|
||||
REQUIRE(jit.Regs()[7] == 0xd665d210);
|
||||
REQUIRE(jit.Regs()[8] == 0xca926f76);
|
||||
REQUIRE(jit.Regs()[9] == 0x4a24b25b);
|
||||
REQUIRE(jit.Regs()[10] == 0xaed44144);
|
||||
REQUIRE(jit.Regs()[11] == 0xe87230b2);
|
||||
REQUIRE(jit.Regs()[12] == 0x98e391de);
|
||||
REQUIRE(jit.Regs()[13] == 0x126efc0c);
|
||||
REQUIRE(jit.Regs()[14] == 0xe591fd11);
|
||||
REQUIRE(jit.Regs()[15] == 0x00000008);
|
||||
REQUIRE(jit.Cpsr() == 0xb0000010);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: vclt.f32 with zero", "[arm][A32]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xf3b93628, // vclt.f32 d3, d24, #0
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.ExtRegs()[48] = 0x3a87d9f1;
|
||||
jit.ExtRegs()[49] = 0x80796dc0;
|
||||
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 2;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.ExtRegs()[6] == 0x00000000);
|
||||
REQUIRE(jit.ExtRegs()[7] == 0x00000000);
|
||||
}
|
||||
|
||||
TEST_CASE("arm: vcvt.s16.f64", "[arm][A32]") {
|
||||
ArmTestEnv test_env;
|
||||
A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xeebe8b45, // vcvt.s16.f64 d8, d8, #6
|
||||
0xeafffffe, // b +#0
|
||||
};
|
||||
|
||||
jit.ExtRegs()[16] = 0x9a7110b0;
|
||||
jit.ExtRegs()[17] = 0xcd78f4e7;
|
||||
|
||||
jit.SetCpsr(0x000001d0); // User-mode
|
||||
|
||||
test_env.ticks_left = 2;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.ExtRegs()[16] == 0xffff8000);
|
||||
REQUIRE(jit.ExtRegs()[17] == 0xffffffff);
|
||||
}
|
||||
159
externals/dynarmic/tests/A32/test_thumb_instructions.cpp
vendored
Executable file
159
externals/dynarmic/tests/A32/test_thumb_instructions.cpp
vendored
Executable file
@@ -0,0 +1,159 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#include <catch.hpp>
|
||||
|
||||
#include <dynarmic/A32/a32.h>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "testenv.h"
|
||||
|
||||
static Dynarmic::A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) {
|
||||
Dynarmic::A32::UserConfig user_config;
|
||||
user_config.callbacks = testenv;
|
||||
return user_config;
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: lsls r0, r1, #2", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0x0088, // lsls r0, r1, #2
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 1;
|
||||
jit.Regs()[1] = 2;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 8);
|
||||
REQUIRE(jit.Regs()[1] == 2);
|
||||
REQUIRE(jit.Regs()[15] == 2);
|
||||
REQUIRE(jit.Cpsr() == 0x00000030);
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: lsls r0, r1, #31", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0x07C8, // lsls r0, r1, #31
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[0] = 1;
|
||||
jit.Regs()[1] = 0xFFFFFFFF;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[0] == 0x80000000);
|
||||
REQUIRE(jit.Regs()[1] == 0xffffffff);
|
||||
REQUIRE(jit.Regs()[15] == 2);
|
||||
REQUIRE(jit.Cpsr() == 0xA0000030); // N, C flags, Thumb, User-mode
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: revsh r4, r3", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xBADC, // revsh r4, r3
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[3] = 0x12345678;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[3] == 0x12345678);
|
||||
REQUIRE(jit.Regs()[4] == 0x00007856);
|
||||
REQUIRE(jit.Regs()[15] == 2);
|
||||
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: ldr r3, [r3, #28]", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0x69DB, // ldr r3, [r3, #28]
|
||||
0xE7FE, // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[3] = 0x12345678;
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[3] == 0x97969594); // Memory location 0x12345694
|
||||
REQUIRE(jit.Regs()[15] == 2);
|
||||
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: blx +#67712", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xF010, 0xEC3E, // blx +#67712
|
||||
0xE7FE // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[14] == (0x4 | 1));
|
||||
REQUIRE(jit.Regs()[15] == 0x10880);
|
||||
REQUIRE(jit.Cpsr() == 0x00000010); // User-mode
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: bl +#234584", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xF039, 0xFA2A, // bl +#234584
|
||||
0xE7FE // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[14] == (0x4 | 1));
|
||||
REQUIRE(jit.Regs()[15] == 0x39458);
|
||||
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
|
||||
}
|
||||
|
||||
TEST_CASE("thumb: bl -#42", "[thumb]") {
|
||||
ThumbTestEnv test_env;
|
||||
Dynarmic::A32::Jit jit{GetUserConfig(&test_env)};
|
||||
test_env.code_mem = {
|
||||
0xF7FF, 0xFFE9, // bl -#42
|
||||
0xE7FE // b +#0
|
||||
};
|
||||
|
||||
jit.Regs()[15] = 0; // PC = 0
|
||||
jit.SetCpsr(0x00000030); // Thumb, User-mode
|
||||
|
||||
test_env.ticks_left = 1;
|
||||
jit.Run();
|
||||
|
||||
REQUIRE(jit.Regs()[14] == (0x4 | 1));
|
||||
REQUIRE(jit.Regs()[15] == 0xFFFFFFD6);
|
||||
REQUIRE(jit.Cpsr() == 0x00000030); // Thumb, User-mode
|
||||
}
|
||||
99
externals/dynarmic/tests/A32/testenv.h
vendored
Executable file
99
externals/dynarmic/tests/A32/testenv.h
vendored
Executable file
@@ -0,0 +1,99 @@
|
||||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2018 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <cstring>
|
||||
#include <map>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include <dynarmic/A32/a32.h>
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
template <typename InstructionType_, u32 infinite_loop>
|
||||
class A32TestEnv final : public Dynarmic::A32::UserCallbacks {
|
||||
public:
|
||||
using InstructionType = InstructionType_;
|
||||
using RegisterArray = std::array<u32, 16>;
|
||||
using ExtRegsArray = std::array<u32, 64>;
|
||||
|
||||
u64 ticks_left = 0;
|
||||
bool code_mem_modified_by_guest = false;
|
||||
std::vector<InstructionType> code_mem;
|
||||
std::map<u32, u8> modified_memory;
|
||||
std::vector<std::string> interrupts;
|
||||
|
||||
std::uint32_t MemoryReadCode(u32 vaddr) override {
|
||||
const size_t index = vaddr / sizeof(InstructionType);
|
||||
if (index < code_mem.size()) {
|
||||
u32 value;
|
||||
std::memcpy(&value, &code_mem[index], sizeof(u32));
|
||||
return value;
|
||||
}
|
||||
return infinite_loop; // B .
|
||||
}
|
||||
|
||||
std::uint8_t MemoryRead8(u32 vaddr) override {
|
||||
if (vaddr < sizeof(InstructionType) * code_mem.size()) {
|
||||
return reinterpret_cast<u8*>(code_mem.data())[vaddr];
|
||||
}
|
||||
if (auto iter = modified_memory.find(vaddr); iter != modified_memory.end()) {
|
||||
return iter->second;
|
||||
}
|
||||
return static_cast<u8>(vaddr);
|
||||
}
|
||||
std::uint16_t MemoryRead16(u32 vaddr) override {
|
||||
return u16(MemoryRead8(vaddr)) | u16(MemoryRead8(vaddr + 1)) << 8;
|
||||
}
|
||||
std::uint32_t MemoryRead32(u32 vaddr) override {
|
||||
return u32(MemoryRead16(vaddr)) | u32(MemoryRead16(vaddr + 2)) << 16;
|
||||
}
|
||||
std::uint64_t MemoryRead64(u32 vaddr) override {
|
||||
return u64(MemoryRead32(vaddr)) | u64(MemoryRead32(vaddr + 4)) << 32;
|
||||
}
|
||||
|
||||
void MemoryWrite8(u32 vaddr, std::uint8_t value) override {
|
||||
if (vaddr < code_mem.size() * sizeof(u32)) {
|
||||
code_mem_modified_by_guest = true;
|
||||
}
|
||||
modified_memory[vaddr] = value;
|
||||
}
|
||||
void MemoryWrite16(u32 vaddr, std::uint16_t value) override {
|
||||
MemoryWrite8(vaddr, static_cast<u8>(value));
|
||||
MemoryWrite8(vaddr + 1, static_cast<u8>(value >> 8));
|
||||
}
|
||||
void MemoryWrite32(u32 vaddr, std::uint32_t value) override {
|
||||
MemoryWrite16(vaddr, static_cast<u16>(value));
|
||||
MemoryWrite16(vaddr + 2, static_cast<u16>(value >> 16));
|
||||
}
|
||||
void MemoryWrite64(u32 vaddr, std::uint64_t value) override {
|
||||
MemoryWrite32(vaddr, static_cast<u32>(value));
|
||||
MemoryWrite32(vaddr + 4, static_cast<u32>(value >> 32));
|
||||
}
|
||||
|
||||
void InterpreterFallback(u32 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:08x}, {}) code = {:08x}", pc, num_instructions, MemoryReadCode(pc)); }
|
||||
|
||||
void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
|
||||
|
||||
void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised({:08x})", pc); }
|
||||
|
||||
void AddTicks(std::uint64_t ticks) override {
|
||||
if (ticks > ticks_left) {
|
||||
ticks_left = 0;
|
||||
return;
|
||||
}
|
||||
ticks_left -= ticks;
|
||||
}
|
||||
std::uint64_t GetTicksRemaining() override {
|
||||
return ticks_left;
|
||||
}
|
||||
};
|
||||
|
||||
using ArmTestEnv = A32TestEnv<u32, 0xEAFFFFFE>;
|
||||
using ThumbTestEnv = A32TestEnv<u16, 0xE7FEE7FE>;
|
||||
13456
externals/dynarmic/tests/A32/vfp_vadd_f32.inc
vendored
Executable file
13456
externals/dynarmic/tests/A32/vfp_vadd_f32.inc
vendored
Executable file
File diff suppressed because it is too large
Load Diff
13456
externals/dynarmic/tests/A32/vfp_vsub_f32.inc
vendored
Executable file
13456
externals/dynarmic/tests/A32/vfp_vsub_f32.inc
vendored
Executable file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user