early-access version 1866
This commit is contained in:
@@ -8,7 +8,6 @@
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#include "core/core.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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@@ -57,53 +56,11 @@ void KeplerCompute::CallMultiMethod(u32 method, const u32* base_start, u32 amoun
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}
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}
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u32 KeplerCompute::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& buffer = launch_description.const_buffer_config[const_buffer];
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u32 result;
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std::memcpy(&result, memory_manager.GetPointer(buffer.Address() + offset), sizeof(u32));
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return result;
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}
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SamplerDescriptor KeplerCompute::AccessBoundSampler(ShaderType stage, u64 offset) const {
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return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
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}
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SamplerDescriptor KeplerCompute::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& tex_info_buffer = launch_description.const_buffer_config[const_buffer];
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const GPUVAddr tex_info_address = tex_info_buffer.Address() + offset;
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return AccessSampler(memory_manager.Read<u32>(tex_info_address));
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}
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SamplerDescriptor KeplerCompute::AccessSampler(u32 handle) const {
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const Texture::TextureHandle tex_handle{handle};
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const Texture::TICEntry tic = GetTICEntry(tex_handle.tic_id);
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const Texture::TSCEntry tsc = GetTSCEntry(tex_handle.tsc_id);
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SamplerDescriptor result = SamplerDescriptor::FromTIC(tic);
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result.is_shadow.Assign(tsc.depth_compare_enabled.Value());
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return result;
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}
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VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() {
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return rasterizer->AccessGuestDriverProfile();
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}
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const VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() const {
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return rasterizer->AccessGuestDriverProfile();
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}
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32));
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const GPUVAddr code_addr = regs.code_loc.Address() + launch_description.program_start;
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LOG_TRACE(HW_GPU, "Compute invocation launched at address 0x{:016x}", code_addr);
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rasterizer->DispatchCompute(code_addr);
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rasterizer->DispatchCompute();
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}
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Texture::TICEntry KeplerCompute::GetTICEntry(u32 tic_index) const {
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@@ -10,10 +10,8 @@
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/engines/const_buffer_engine_interface.h"
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#include "video_core/engines/engine_interface.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/gpu.h"
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#include "video_core/textures/texture.h"
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@@ -40,7 +38,7 @@ namespace Tegra::Engines {
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#define KEPLER_COMPUTE_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
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class KeplerCompute final : public ConstBufferEngineInterface, public EngineInterface {
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class KeplerCompute final : public EngineInterface {
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public:
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explicit KeplerCompute(Core::System& system, MemoryManager& memory_manager);
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~KeplerCompute();
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@@ -209,23 +207,6 @@ public:
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const override;
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SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const override;
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SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const override;
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SamplerDescriptor AccessSampler(u32 handle) const override;
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u32 GetBoundBuffer() const override {
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return regs.tex_cb_index;
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}
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VideoCore::GuestDriverProfile& AccessGuestDriverProfile() override;
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const VideoCore::GuestDriverProfile& AccessGuestDriverProfile() const override;
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private:
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void ProcessLaunch();
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@@ -8,7 +8,6 @@
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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@@ -670,42 +669,4 @@ void Maxwell3D::ProcessClearBuffers() {
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rasterizer->Clear();
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}
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u32 Maxwell3D::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
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ASSERT(stage != ShaderType::Compute);
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const auto& shader_stage = state.shader_stages[static_cast<std::size_t>(stage)];
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const auto& buffer = shader_stage.const_buffers[const_buffer];
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return memory_manager.Read<u32>(buffer.address + offset);
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}
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SamplerDescriptor Maxwell3D::AccessBoundSampler(ShaderType stage, u64 offset) const {
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return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
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}
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SamplerDescriptor Maxwell3D::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const {
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ASSERT(stage != ShaderType::Compute);
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const auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
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const auto& tex_info_buffer = shader.const_buffers[const_buffer];
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const GPUVAddr tex_info_address = tex_info_buffer.address + offset;
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return AccessSampler(memory_manager.Read<u32>(tex_info_address));
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}
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SamplerDescriptor Maxwell3D::AccessSampler(u32 handle) const {
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const Texture::TextureHandle tex_handle{handle};
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const Texture::TICEntry tic = GetTICEntry(tex_handle.tic_id);
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const Texture::TSCEntry tsc = GetTSCEntry(tex_handle.tsc_id);
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SamplerDescriptor result = SamplerDescriptor::FromTIC(tic);
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result.is_shadow.Assign(tsc.depth_compare_enabled.Value());
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return result;
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}
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VideoCore::GuestDriverProfile& Maxwell3D::AccessGuestDriverProfile() {
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return rasterizer->AccessGuestDriverProfile();
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}
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const VideoCore::GuestDriverProfile& Maxwell3D::AccessGuestDriverProfile() const {
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return rasterizer->AccessGuestDriverProfile();
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}
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} // namespace Tegra::Engines
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@@ -17,11 +17,9 @@
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/math_util.h"
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#include "video_core/engines/const_buffer_engine_interface.h"
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#include "video_core/engines/const_buffer_info.h"
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#include "video_core/engines/engine_interface.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/gpu.h"
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#include "video_core/macro/macro.h"
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#include "video_core/textures/texture.h"
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@@ -49,7 +47,7 @@ namespace Tegra::Engines {
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#define MAXWELL3D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Maxwell3D::Regs, field_name) / sizeof(u32))
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class Maxwell3D final : public ConstBufferEngineInterface, public EngineInterface {
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class Maxwell3D final : public EngineInterface {
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public:
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explicit Maxwell3D(Core::System& system, MemoryManager& memory_manager);
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~Maxwell3D();
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@@ -307,10 +305,6 @@ public:
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return (type == Type::SignedNorm) || (type == Type::UnsignedNorm);
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}
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bool IsConstant() const {
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return constant;
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}
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bool IsValid() const {
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return size != Size::Invalid;
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}
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@@ -912,7 +906,11 @@ public:
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u32 fill_rectangle;
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INSERT_PADDING_WORDS_NOINIT(0x8);
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INSERT_PADDING_WORDS_NOINIT(0x2);
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u32 conservative_raster_enable;
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INSERT_PADDING_WORDS_NOINIT(0x5);
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std::array<VertexAttribute, NumVertexAttributes> vertex_attrib_format;
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@@ -959,7 +957,11 @@ public:
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SamplerIndex sampler_index;
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INSERT_PADDING_WORDS_NOINIT(0x25);
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INSERT_PADDING_WORDS_NOINIT(0x2);
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std::array<u32, 8> gp_passthrough_mask;
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INSERT_PADDING_WORDS_NOINIT(0x1B);
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u32 depth_test_enable;
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@@ -1152,7 +1154,11 @@ public:
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u32 index;
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} primitive_restart;
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INSERT_PADDING_WORDS_NOINIT(0x5F);
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INSERT_PADDING_WORDS_NOINIT(0xE);
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u32 provoking_vertex_last;
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INSERT_PADDING_WORDS_NOINIT(0x50);
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struct {
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u32 start_addr_high;
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@@ -1424,23 +1430,6 @@ public:
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void FlushMMEInlineDraw();
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u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const override;
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SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const override;
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SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const override;
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SamplerDescriptor AccessSampler(u32 handle) const override;
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u32 GetBoundBuffer() const override {
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return regs.tex_cb_index;
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}
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VideoCore::GuestDriverProfile& AccessGuestDriverProfile() override;
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const VideoCore::GuestDriverProfile& AccessGuestDriverProfile() const override;
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bool ShouldExecute() const {
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return execute_on;
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}
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@@ -1630,6 +1619,7 @@ ASSERT_REG_POSITION(zeta, 0x3F8);
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ASSERT_REG_POSITION(render_area, 0x3FD);
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ASSERT_REG_POSITION(clear_flags, 0x43E);
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ASSERT_REG_POSITION(fill_rectangle, 0x44F);
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ASSERT_REG_POSITION(conservative_raster_enable, 0x452);
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ASSERT_REG_POSITION(vertex_attrib_format, 0x458);
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ASSERT_REG_POSITION(multisample_sample_locations, 0x478);
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ASSERT_REG_POSITION(multisample_coverage_to_color, 0x47E);
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@@ -1638,6 +1628,7 @@ ASSERT_REG_POSITION(zeta_width, 0x48a);
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ASSERT_REG_POSITION(zeta_height, 0x48b);
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ASSERT_REG_POSITION(zeta_depth, 0x48c);
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ASSERT_REG_POSITION(sampler_index, 0x48D);
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ASSERT_REG_POSITION(gp_passthrough_mask, 0x490);
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ASSERT_REG_POSITION(depth_test_enable, 0x4B3);
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ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
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ASSERT_REG_POSITION(depth_write_enabled, 0x4BA);
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@@ -1690,6 +1681,7 @@ ASSERT_REG_POSITION(point_coord_replace, 0x581);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(primitive_restart, 0x591);
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ASSERT_REG_POSITION(provoking_vertex_last, 0x5A1);
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ASSERT_REG_POSITION(index_array, 0x5F2);
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ASSERT_REG_POSITION(polygon_offset_clamp, 0x61F);
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ASSERT_REG_POSITION(instanced_arrays, 0x620);
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@@ -99,7 +99,8 @@ void MaxwellDMA::CopyBlockLinearToPitch() {
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// Optimized path for micro copies.
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const size_t dst_size = static_cast<size_t>(regs.pitch_out) * regs.line_count;
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if (dst_size < GOB_SIZE && regs.pitch_out <= GOB_SIZE_X) {
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if (dst_size < GOB_SIZE && regs.pitch_out <= GOB_SIZE_X &&
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regs.src_params.height > GOB_SIZE_Y) {
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FastCopyBlockLinearToPitch();
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return;
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}
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