early-access version 1358
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@@ -1243,9 +1243,15 @@ typename BufferCache<P>::Binding BufferCache<P>::StorageBufferBinding(GPUVAddr s
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if (!cpu_addr || size == 0) {
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return NULL_BINDING;
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}
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// HACK(Rodrigo): This is the number of bytes bound in host beyond the guest API's range.
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// It exists due to some games like Astral Chain operate out of bounds.
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// Binding the whole map range would be technically correct, but games have large maps that make
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// this approach unaffordable for now.
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static constexpr u32 arbitrary_extra_bytes = 0xc000;
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const u32 bytes_to_map_end = static_cast<u32>(gpu_memory.BytesToMapEnd(gpu_addr));
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const Binding binding{
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.cpu_addr = *cpu_addr,
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.size = size,
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.size = std::min(size + arbitrary_extra_bytes, bytes_to_map_end),
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.buffer_id = BufferId{},
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};
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return binding;
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@@ -4,6 +4,7 @@
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/hle/kernel/memory/page_table.h"
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#include "core/hle/kernel/process.h"
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@@ -38,6 +39,12 @@ GPUVAddr MemoryManager::UpdateRange(GPUVAddr gpu_addr, PageEntry page_entry, std
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}
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GPUVAddr MemoryManager::Map(VAddr cpu_addr, GPUVAddr gpu_addr, std::size_t size) {
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const auto it = std::ranges::lower_bound(map_ranges, gpu_addr, {}, &MapRange::first);
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if (it != map_ranges.end() && it->first == gpu_addr) {
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it->second = size;
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} else {
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map_ranges.insert(it, MapRange{gpu_addr, size});
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}
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return UpdateRange(gpu_addr, cpu_addr, size);
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}
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@@ -52,10 +59,16 @@ GPUVAddr MemoryManager::MapAllocate32(VAddr cpu_addr, std::size_t size) {
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}
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void MemoryManager::Unmap(GPUVAddr gpu_addr, std::size_t size) {
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if (!size) {
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if (size == 0) {
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return;
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}
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const auto it = std::ranges::lower_bound(map_ranges, gpu_addr, {}, &MapRange::first);
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if (it != map_ranges.end()) {
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ASSERT(it->first == gpu_addr);
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map_ranges.erase(it);
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} else {
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UNREACHABLE_MSG("Unmapping non-existent GPU address=0x{:x}", gpu_addr);
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}
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// Flush and invalidate through the GPU interface, to be asynchronous if possible.
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const std::optional<VAddr> cpu_addr = GpuToCpuAddress(gpu_addr);
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ASSERT(cpu_addr);
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@@ -237,6 +250,12 @@ const u8* MemoryManager::GetPointer(GPUVAddr gpu_addr) const {
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return system.Memory().GetPointer(*address);
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}
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size_t MemoryManager::BytesToMapEnd(GPUVAddr gpu_addr) const noexcept {
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auto it = std::ranges::upper_bound(map_ranges, gpu_addr, {}, &MapRange::first);
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--it;
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return it->second - (gpu_addr - it->first);
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}
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void MemoryManager::ReadBlock(GPUVAddr gpu_src_addr, void* dest_buffer, std::size_t size) const {
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std::size_t remaining_size{size};
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std::size_t page_index{gpu_src_addr >> page_bits};
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@@ -85,6 +85,9 @@ public:
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[[nodiscard]] u8* GetPointer(GPUVAddr addr);
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[[nodiscard]] const u8* GetPointer(GPUVAddr addr) const;
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/// Returns the number of bytes until the end of the memory map containing the given GPU address
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[[nodiscard]] size_t BytesToMapEnd(GPUVAddr gpu_addr) const noexcept;
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/**
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* ReadBlock and WriteBlock are full read and write operations over virtual
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* GPU Memory. It's important to use these when GPU memory may not be continuous
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@@ -160,6 +163,9 @@ private:
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std::vector<PageEntry> page_table;
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std::vector<std::pair<VAddr, std::size_t>> cache_invalidate_queue;
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using MapRange = std::pair<GPUVAddr, size_t>;
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std::vector<MapRange> map_ranges;
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};
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} // namespace Tegra
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@@ -465,6 +465,14 @@ public:
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return operands.size();
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}
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NodeBlock& GetOperands() {
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return operands;
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}
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const NodeBlock& GetOperands() const {
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return operands;
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}
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[[nodiscard]] const Node& operator[](std::size_t operand_index) const {
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return operands.at(operand_index);
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}
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@@ -388,9 +388,54 @@ void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_
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if (!sets_cc) {
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return;
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}
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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switch (value->index()) {
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case 0: // Operation Node
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SearchOperands(bb, value);
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break;
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case 2: // Genral Purpose Node
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if (const auto* gpr = std::get_if<GprNode>(value.get())) {
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LOG_DEBUG(HW_GPU, "GprNode: index={}", gpr->GetIndex());
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value),
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Immediate(gpr->GetIndex()));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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}
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break;
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default:
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Node Type: {}", value->index());
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break;
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}
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}
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void ShaderIR::SearchOperands(NodeBlock& nb, Node var) {
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const auto* op = std::get_if<OperationNode>(var.get());
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if (op == nullptr) {
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return;
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}
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if (op->GetOperandsCount() == 0) {
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return;
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}
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for (auto& operand : op->GetOperands()) {
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switch (operand->index()) {
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case 0: // Operation Node
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return SearchOperands(nb, operand);
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case 2: // General Purpose Node
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if (const auto* gpr = std::get_if<GprNode>(operand.get())) {
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LOG_DEBUG(HW_GPU, "Child GprNode: index={}", gpr->GetIndex());
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(operand),
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Immediate(gpr->GetIndex()));
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SetInternalFlag(nb, InternalFlag::Zero, std::move(zerop));
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}
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break;
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default:
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LOG_WARNING(HW_GPU, "Child Node Type: {}", operand->index());
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break;
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}
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}
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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@@ -350,6 +350,9 @@ private:
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/// Access a bindless image sampler.
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ImageEntry& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type);
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/// Recursive Iteration over the OperationNode operands, searching for GprNodes.
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void SearchOperands(NodeBlock& nb, Node var);
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/// Extracts a sequence of bits from a node
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Node BitfieldExtract(Node value, u32 offset, u32 bits);
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