early-access version 2097
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@@ -48,8 +48,9 @@ void nvdisp_disp0::flip(u32 buffer_handle, u32 offset, u32 format, u32 width, u3
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addr, offset, width, height, stride, format);
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const auto pixel_format = static_cast<Tegra::FramebufferConfig::PixelFormat>(format);
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const Tegra::FramebufferConfig framebuffer{addr, offset, width, height,
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stride, pixel_format, transform, crop_rect};
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const auto transform_flags = static_cast<Tegra::FramebufferConfig::TransformFlags>(transform);
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const Tegra::FramebufferConfig framebuffer{addr, offset, width, height,
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stride, pixel_format, transform_flags, crop_rect};
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system.GetPerfStats().EndSystemFrame();
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system.GPU().SwapBuffers(&framebuffer);
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@@ -111,7 +111,6 @@ NvResult nvhost_ctrl::IocCtrlEventWait(const std::vector<u8>& input, std::vector
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event.event->GetWritableEvent().Signal();
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return NvResult::Success;
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}
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auto lock = gpu.LockSync();
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const u32 current_syncpoint_value = event.fence.value;
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const s32 diff = current_syncpoint_value - params.threshold;
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if (diff >= 0) {
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@@ -132,23 +131,24 @@ NvResult nvhost_ctrl::IocCtrlEventWait(const std::vector<u8>& input, std::vector
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}
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EventState status = events_interface.status[event_id];
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if (event_id < MaxNvEvents || status == EventState::Free || status == EventState::Registered) {
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events_interface.SetEventStatus(event_id, EventState::Waiting);
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events_interface.assigned_syncpt[event_id] = params.syncpt_id;
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events_interface.assigned_value[event_id] = target_value;
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if (is_async) {
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params.value = params.syncpt_id << 4;
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} else {
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params.value = ((params.syncpt_id & 0xfff) << 16) | 0x10000000;
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}
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params.value |= event_id;
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event.event->GetWritableEvent().Clear();
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gpu.RegisterSyncptInterrupt(params.syncpt_id, target_value);
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const bool bad_parameter = status != EventState::Free && status != EventState::Registered;
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if (bad_parameter) {
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std::memcpy(output.data(), ¶ms, sizeof(params));
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return NvResult::Timeout;
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return NvResult::BadParameter;
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}
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events_interface.SetEventStatus(event_id, EventState::Waiting);
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events_interface.assigned_syncpt[event_id] = params.syncpt_id;
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events_interface.assigned_value[event_id] = target_value;
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if (is_async) {
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params.value = params.syncpt_id << 4;
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} else {
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params.value = ((params.syncpt_id & 0xfff) << 16) | 0x10000000;
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}
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params.value |= event_id;
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event.event->GetWritableEvent().Clear();
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gpu.RegisterSyncptInterrupt(params.syncpt_id, target_value);
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std::memcpy(output.data(), ¶ms, sizeof(params));
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return NvResult::BadParameter;
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return NvResult::Timeout;
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}
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NvResult nvhost_ctrl::IocCtrlEventRegister(const std::vector<u8>& input, std::vector<u8>& output) {
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@@ -13,6 +13,14 @@
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#include "video_core/memory_manager.h"
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namespace Service::Nvidia::Devices {
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namespace {
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Tegra::CommandHeader BuildFenceAction(Tegra::GPU::FenceOperation op, u32 syncpoint_id) {
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Tegra::GPU::FenceAction result{};
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result.op.Assign(op);
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result.syncpoint_id.Assign(syncpoint_id);
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return {result.raw};
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}
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} // namespace
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nvhost_gpu::nvhost_gpu(Core::System& system_, std::shared_ptr<nvmap> nvmap_dev_,
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SyncpointManager& syncpoint_manager_)
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@@ -187,7 +195,7 @@ static std::vector<Tegra::CommandHeader> BuildWaitCommandList(Fence fence) {
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{fence.value},
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Tegra::BuildCommandHeader(Tegra::BufferMethods::FenceAction, 1,
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Tegra::SubmissionMode::Increasing),
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Tegra::GPU::FenceAction::Build(Tegra::GPU::FenceOperation::Acquire, fence.id),
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BuildFenceAction(Tegra::GPU::FenceOperation::Acquire, fence.id),
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};
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}
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@@ -200,8 +208,7 @@ static std::vector<Tegra::CommandHeader> BuildIncrementCommandList(Fence fence,
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for (u32 count = 0; count < add_increment; ++count) {
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result.emplace_back(Tegra::BuildCommandHeader(Tegra::BufferMethods::FenceAction, 1,
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Tegra::SubmissionMode::Increasing));
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result.emplace_back(
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Tegra::GPU::FenceAction::Build(Tegra::GPU::FenceOperation::Increment, fence.id));
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result.emplace_back(BuildFenceAction(Tegra::GPU::FenceOperation::Increment, fence.id));
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}
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return result;
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