another try
This commit is contained in:
mgthepro
@@ -1,122 +1,122 @@
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// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cstring>
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#include <fstream>
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#include <optional>
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#include <span>
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#include <boost/container_hash/hash.hpp>
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#include <fstream>
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#include "common/assert.h"
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#include "common/fs/fs.h"
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#include "common/fs/path_util.h"
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#include "common/settings.h"
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#include "video_core/macro/macro.h"
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#include "video_core/macro/macro_hle.h"
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#include "video_core/macro/macro_interpreter.h"
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#include "video_core/macro/macro_jit_x64.h"
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namespace Tegra {
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static void Dump(u64 hash, std::span<const u32> code) {
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const auto base_dir{Common::FS::GetYuzuPath(Common::FS::YuzuPath::DumpDir)};
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const auto macro_dir{base_dir / "macros"};
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if (!Common::FS::CreateDir(base_dir) || !Common::FS::CreateDir(macro_dir)) {
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LOG_ERROR(Common_Filesystem, "Failed to create macro dump directories");
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return;
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}
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const auto name{macro_dir / fmt::format("{:016x}.macro", hash)};
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std::fstream macro_file(name, std::ios::out | std::ios::binary);
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if (!macro_file) {
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LOG_ERROR(Common_Filesystem, "Unable to open or create file at {}",
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Common::FS::PathToUTF8String(name));
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return;
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}
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macro_file.write(reinterpret_cast<const char*>(code.data()), code.size_bytes());
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}
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MacroEngine::MacroEngine(Engines::Maxwell3D& maxwell3d)
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: hle_macros{std::make_unique<Tegra::HLEMacro>(maxwell3d)} {}
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MacroEngine::~MacroEngine() = default;
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void MacroEngine::AddCode(u32 method, u32 data) {
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uploaded_macro_code[method].push_back(data);
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}
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void MacroEngine::ClearCode(u32 method) {
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macro_cache.erase(method);
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uploaded_macro_code.erase(method);
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}
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void MacroEngine::Execute(u32 method, const std::vector<u32>& parameters) {
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auto compiled_macro = macro_cache.find(method);
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if (compiled_macro != macro_cache.end()) {
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const auto& cache_info = compiled_macro->second;
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if (cache_info.has_hle_program) {
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cache_info.hle_program->Execute(parameters, method);
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} else {
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cache_info.lle_program->Execute(parameters, method);
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}
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} else {
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// Macro not compiled, check if it's uploaded and if so, compile it
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std::optional<u32> mid_method;
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const auto macro_code = uploaded_macro_code.find(method);
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if (macro_code == uploaded_macro_code.end()) {
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for (const auto& [method_base, code] : uploaded_macro_code) {
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if (method >= method_base && (method - method_base) < code.size()) {
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mid_method = method_base;
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break;
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}
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}
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if (!mid_method.has_value()) {
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ASSERT_MSG(false, "Macro 0x{0:x} was not uploaded", method);
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return;
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}
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}
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auto& cache_info = macro_cache[method];
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if (!mid_method.has_value()) {
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cache_info.lle_program = Compile(macro_code->second);
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cache_info.hash = boost::hash_value(macro_code->second);
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if (Settings::values.dump_macros) {
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Dump(cache_info.hash, macro_code->second);
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}
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} else {
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const auto& macro_cached = uploaded_macro_code[mid_method.value()];
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const auto rebased_method = method - mid_method.value();
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auto& code = uploaded_macro_code[method];
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code.resize(macro_cached.size() - rebased_method);
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std::memcpy(code.data(), macro_cached.data() + rebased_method,
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code.size() * sizeof(u32));
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cache_info.hash = boost::hash_value(code);
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cache_info.lle_program = Compile(code);
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if (Settings::values.dump_macros) {
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Dump(cache_info.hash, code);
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}
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}
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if (auto hle_program = hle_macros->GetHLEProgram(cache_info.hash)) {
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cache_info.has_hle_program = true;
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cache_info.hle_program = std::move(hle_program);
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cache_info.hle_program->Execute(parameters, method);
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} else {
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cache_info.lle_program->Execute(parameters, method);
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}
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}
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}
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std::unique_ptr<MacroEngine> GetMacroEngine(Engines::Maxwell3D& maxwell3d) {
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if (Settings::values.disable_macro_jit) {
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return std::make_unique<MacroInterpreter>(maxwell3d);
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}
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#ifdef ARCHITECTURE_x86_64
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return std::make_unique<MacroJITx64>(maxwell3d);
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#else
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return std::make_unique<MacroInterpreter>(maxwell3d);
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#endif
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}
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} // namespace Tegra
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// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cstring>
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#include <fstream>
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#include <optional>
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#include <span>
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#include <boost/container_hash/hash.hpp>
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#include <fstream>
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#include "common/assert.h"
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#include "common/fs/fs.h"
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#include "common/fs/path_util.h"
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#include "common/settings.h"
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#include "video_core/macro/macro.h"
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#include "video_core/macro/macro_hle.h"
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#include "video_core/macro/macro_interpreter.h"
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#include "video_core/macro/macro_jit_x64.h"
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namespace Tegra {
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static void Dump(u64 hash, std::span<const u32> code) {
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const auto base_dir{Common::FS::GetYuzuPath(Common::FS::YuzuPath::DumpDir)};
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const auto macro_dir{base_dir / "macros"};
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if (!Common::FS::CreateDir(base_dir) || !Common::FS::CreateDir(macro_dir)) {
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LOG_ERROR(Common_Filesystem, "Failed to create macro dump directories");
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return;
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}
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const auto name{macro_dir / fmt::format("{:016x}.macro", hash)};
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std::fstream macro_file(name, std::ios::out | std::ios::binary);
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if (!macro_file) {
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LOG_ERROR(Common_Filesystem, "Unable to open or create file at {}",
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Common::FS::PathToUTF8String(name));
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return;
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}
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macro_file.write(reinterpret_cast<const char*>(code.data()), code.size_bytes());
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}
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MacroEngine::MacroEngine(Engines::Maxwell3D& maxwell3d)
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: hle_macros{std::make_unique<Tegra::HLEMacro>(maxwell3d)} {}
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MacroEngine::~MacroEngine() = default;
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void MacroEngine::AddCode(u32 method, u32 data) {
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uploaded_macro_code[method].push_back(data);
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}
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void MacroEngine::ClearCode(u32 method) {
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macro_cache.erase(method);
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uploaded_macro_code.erase(method);
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}
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void MacroEngine::Execute(u32 method, const std::vector<u32>& parameters) {
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auto compiled_macro = macro_cache.find(method);
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if (compiled_macro != macro_cache.end()) {
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const auto& cache_info = compiled_macro->second;
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if (cache_info.has_hle_program) {
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cache_info.hle_program->Execute(parameters, method);
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} else {
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cache_info.lle_program->Execute(parameters, method);
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}
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} else {
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// Macro not compiled, check if it's uploaded and if so, compile it
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std::optional<u32> mid_method;
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const auto macro_code = uploaded_macro_code.find(method);
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if (macro_code == uploaded_macro_code.end()) {
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for (const auto& [method_base, code] : uploaded_macro_code) {
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if (method >= method_base && (method - method_base) < code.size()) {
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mid_method = method_base;
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break;
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}
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}
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if (!mid_method.has_value()) {
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ASSERT_MSG(false, "Macro 0x{0:x} was not uploaded", method);
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return;
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}
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}
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auto& cache_info = macro_cache[method];
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if (!mid_method.has_value()) {
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cache_info.lle_program = Compile(macro_code->second);
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cache_info.hash = boost::hash_value(macro_code->second);
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if (Settings::values.dump_macros) {
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Dump(cache_info.hash, macro_code->second);
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}
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} else {
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const auto& macro_cached = uploaded_macro_code[mid_method.value()];
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const auto rebased_method = method - mid_method.value();
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auto& code = uploaded_macro_code[method];
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code.resize(macro_cached.size() - rebased_method);
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std::memcpy(code.data(), macro_cached.data() + rebased_method,
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code.size() * sizeof(u32));
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cache_info.hash = boost::hash_value(code);
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cache_info.lle_program = Compile(code);
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if (Settings::values.dump_macros) {
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Dump(cache_info.hash, code);
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}
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}
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if (auto hle_program = hle_macros->GetHLEProgram(cache_info.hash)) {
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cache_info.has_hle_program = true;
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cache_info.hle_program = std::move(hle_program);
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cache_info.hle_program->Execute(parameters, method);
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} else {
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cache_info.lle_program->Execute(parameters, method);
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}
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}
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}
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std::unique_ptr<MacroEngine> GetMacroEngine(Engines::Maxwell3D& maxwell3d) {
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if (Settings::values.disable_macro_jit) {
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return std::make_unique<MacroInterpreter>(maxwell3d);
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}
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#ifdef ARCHITECTURE_x86_64
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return std::make_unique<MacroJITx64>(maxwell3d);
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#else
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return std::make_unique<MacroInterpreter>(maxwell3d);
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#endif
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}
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} // namespace Tegra
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@@ -1,144 +1,144 @@
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// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D;
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}
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namespace Macro {
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constexpr std::size_t NUM_MACRO_REGISTERS = 8;
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enum class Operation : u32 {
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ALU = 0,
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AddImmediate = 1,
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ExtractInsert = 2,
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ExtractShiftLeftImmediate = 3,
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ExtractShiftLeftRegister = 4,
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Read = 5,
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Unused = 6, // This operation doesn't seem to be a valid encoding.
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Branch = 7,
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};
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enum class ALUOperation : u32 {
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Add = 0,
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AddWithCarry = 1,
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Subtract = 2,
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SubtractWithBorrow = 3,
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// Operations 4-7 don't seem to be valid encodings.
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Xor = 8,
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Or = 9,
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And = 10,
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AndNot = 11,
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Nand = 12
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};
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enum class ResultOperation : u32 {
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IgnoreAndFetch = 0,
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Move = 1,
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MoveAndSetMethod = 2,
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FetchAndSend = 3,
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MoveAndSend = 4,
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FetchAndSetMethod = 5,
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MoveAndSetMethodFetchAndSend = 6,
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MoveAndSetMethodSend = 7
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};
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enum class BranchCondition : u32 {
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Zero = 0,
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NotZero = 1,
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};
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union Opcode {
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u32 raw;
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BitField<0, 3, Operation> operation;
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BitField<4, 3, ResultOperation> result_operation;
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BitField<4, 1, BranchCondition> branch_condition;
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// If set on a branch, then the branch doesn't have a delay slot.
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BitField<5, 1, u32> branch_annul;
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BitField<7, 1, u32> is_exit;
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BitField<8, 3, u32> dst;
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BitField<11, 3, u32> src_a;
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BitField<14, 3, u32> src_b;
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// The signed immediate overlaps the second source operand and the alu operation.
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BitField<14, 18, s32> immediate;
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BitField<17, 5, ALUOperation> alu_operation;
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// Bitfield instructions data
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BitField<17, 5, u32> bf_src_bit;
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BitField<22, 5, u32> bf_size;
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BitField<27, 5, u32> bf_dst_bit;
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u32 GetBitfieldMask() const {
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return (1 << bf_size) - 1;
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}
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s32 GetBranchTarget() const {
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return static_cast<s32>(immediate * sizeof(u32));
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}
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};
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union MethodAddress {
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u32 raw;
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BitField<0, 12, u32> address;
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BitField<12, 6, u32> increment;
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};
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} // namespace Macro
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class HLEMacro;
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class CachedMacro {
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public:
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virtual ~CachedMacro() = default;
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/**
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* Executes the macro code with the specified input parameters.
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*
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* @param parameters The parameters of the macro
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* @param method The method to execute
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*/
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virtual void Execute(const std::vector<u32>& parameters, u32 method) = 0;
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};
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class MacroEngine {
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public:
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explicit MacroEngine(Engines::Maxwell3D& maxwell3d);
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virtual ~MacroEngine();
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// Store the uploaded macro code to compile them when they're called.
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void AddCode(u32 method, u32 data);
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// Clear the code associated with a method.
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void ClearCode(u32 method);
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// Compiles the macro if its not in the cache, and executes the compiled macro
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void Execute(u32 method, const std::vector<u32>& parameters);
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protected:
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virtual std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) = 0;
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private:
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struct CacheInfo {
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std::unique_ptr<CachedMacro> lle_program{};
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std::unique_ptr<CachedMacro> hle_program{};
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u64 hash{};
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bool has_hle_program{};
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};
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std::unordered_map<u32, CacheInfo> macro_cache;
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std::unordered_map<u32, std::vector<u32>> uploaded_macro_code;
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std::unique_ptr<HLEMacro> hle_macros;
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};
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std::unique_ptr<MacroEngine> GetMacroEngine(Engines::Maxwell3D& maxwell3d);
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||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
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||||
|
||||
#include <memory>
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#include <unordered_map>
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#include <vector>
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Engines {
|
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class Maxwell3D;
|
||||
}
|
||||
|
||||
namespace Macro {
|
||||
constexpr std::size_t NUM_MACRO_REGISTERS = 8;
|
||||
enum class Operation : u32 {
|
||||
ALU = 0,
|
||||
AddImmediate = 1,
|
||||
ExtractInsert = 2,
|
||||
ExtractShiftLeftImmediate = 3,
|
||||
ExtractShiftLeftRegister = 4,
|
||||
Read = 5,
|
||||
Unused = 6, // This operation doesn't seem to be a valid encoding.
|
||||
Branch = 7,
|
||||
};
|
||||
|
||||
enum class ALUOperation : u32 {
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Add = 0,
|
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AddWithCarry = 1,
|
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Subtract = 2,
|
||||
SubtractWithBorrow = 3,
|
||||
// Operations 4-7 don't seem to be valid encodings.
|
||||
Xor = 8,
|
||||
Or = 9,
|
||||
And = 10,
|
||||
AndNot = 11,
|
||||
Nand = 12
|
||||
};
|
||||
|
||||
enum class ResultOperation : u32 {
|
||||
IgnoreAndFetch = 0,
|
||||
Move = 1,
|
||||
MoveAndSetMethod = 2,
|
||||
FetchAndSend = 3,
|
||||
MoveAndSend = 4,
|
||||
FetchAndSetMethod = 5,
|
||||
MoveAndSetMethodFetchAndSend = 6,
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||||
MoveAndSetMethodSend = 7
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||||
};
|
||||
|
||||
enum class BranchCondition : u32 {
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||||
Zero = 0,
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||||
NotZero = 1,
|
||||
};
|
||||
|
||||
union Opcode {
|
||||
u32 raw;
|
||||
BitField<0, 3, Operation> operation;
|
||||
BitField<4, 3, ResultOperation> result_operation;
|
||||
BitField<4, 1, BranchCondition> branch_condition;
|
||||
// If set on a branch, then the branch doesn't have a delay slot.
|
||||
BitField<5, 1, u32> branch_annul;
|
||||
BitField<7, 1, u32> is_exit;
|
||||
BitField<8, 3, u32> dst;
|
||||
BitField<11, 3, u32> src_a;
|
||||
BitField<14, 3, u32> src_b;
|
||||
// The signed immediate overlaps the second source operand and the alu operation.
|
||||
BitField<14, 18, s32> immediate;
|
||||
|
||||
BitField<17, 5, ALUOperation> alu_operation;
|
||||
|
||||
// Bitfield instructions data
|
||||
BitField<17, 5, u32> bf_src_bit;
|
||||
BitField<22, 5, u32> bf_size;
|
||||
BitField<27, 5, u32> bf_dst_bit;
|
||||
|
||||
u32 GetBitfieldMask() const {
|
||||
return (1 << bf_size) - 1;
|
||||
}
|
||||
|
||||
s32 GetBranchTarget() const {
|
||||
return static_cast<s32>(immediate * sizeof(u32));
|
||||
}
|
||||
};
|
||||
|
||||
union MethodAddress {
|
||||
u32 raw;
|
||||
BitField<0, 12, u32> address;
|
||||
BitField<12, 6, u32> increment;
|
||||
};
|
||||
|
||||
} // namespace Macro
|
||||
|
||||
class HLEMacro;
|
||||
|
||||
class CachedMacro {
|
||||
public:
|
||||
virtual ~CachedMacro() = default;
|
||||
/**
|
||||
* Executes the macro code with the specified input parameters.
|
||||
*
|
||||
* @param parameters The parameters of the macro
|
||||
* @param method The method to execute
|
||||
*/
|
||||
virtual void Execute(const std::vector<u32>& parameters, u32 method) = 0;
|
||||
};
|
||||
|
||||
class MacroEngine {
|
||||
public:
|
||||
explicit MacroEngine(Engines::Maxwell3D& maxwell3d);
|
||||
virtual ~MacroEngine();
|
||||
|
||||
// Store the uploaded macro code to compile them when they're called.
|
||||
void AddCode(u32 method, u32 data);
|
||||
|
||||
// Clear the code associated with a method.
|
||||
void ClearCode(u32 method);
|
||||
|
||||
// Compiles the macro if its not in the cache, and executes the compiled macro
|
||||
void Execute(u32 method, const std::vector<u32>& parameters);
|
||||
|
||||
protected:
|
||||
virtual std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) = 0;
|
||||
|
||||
private:
|
||||
struct CacheInfo {
|
||||
std::unique_ptr<CachedMacro> lle_program{};
|
||||
std::unique_ptr<CachedMacro> hle_program{};
|
||||
u64 hash{};
|
||||
bool has_hle_program{};
|
||||
};
|
||||
|
||||
std::unordered_map<u32, CacheInfo> macro_cache;
|
||||
std::unordered_map<u32, std::vector<u32>> uploaded_macro_code;
|
||||
std::unique_ptr<HLEMacro> hle_macros;
|
||||
};
|
||||
|
||||
std::unique_ptr<MacroEngine> GetMacroEngine(Engines::Maxwell3D& maxwell3d);
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
@@ -1,164 +1,164 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include <array>
|
||||
#include <vector>
|
||||
#include "common/scope_exit.h"
|
||||
#include "video_core/dirty_flags.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
#include "video_core/macro/macro_hle.h"
|
||||
#include "video_core/rasterizer_interface.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace {
|
||||
|
||||
using HLEFunction = void (*)(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters);
|
||||
|
||||
// HLE'd functions
|
||||
void HLE_771BB18C62444DA0(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = parameters[2] & maxwell3d.GetRegisterValue(0xD1B);
|
||||
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0] & 0x3ffffff));
|
||||
maxwell3d.regs.global_base_instance_index = parameters[5];
|
||||
maxwell3d.regs.global_base_vertex_index = parameters[3];
|
||||
maxwell3d.regs.index_buffer.count = parameters[1];
|
||||
maxwell3d.regs.index_buffer.first = parameters[4];
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
}
|
||||
|
||||
void HLE_0D61FC9FAAC9FCAD(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
|
||||
maxwell3d.regs.vertex_buffer.first = parameters[3];
|
||||
maxwell3d.regs.vertex_buffer.count = parameters[1];
|
||||
maxwell3d.regs.global_base_instance_index = parameters[4];
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(false, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_buffer.count = 0;
|
||||
}
|
||||
|
||||
void HLE_0217920100488FF7(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
const u32 element_base = parameters[4];
|
||||
const u32 base_instance = parameters[5];
|
||||
maxwell3d.regs.index_buffer.first = parameters[3];
|
||||
maxwell3d.regs.vertex_id_base = element_base;
|
||||
maxwell3d.regs.index_buffer.count = parameters[1];
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.regs.global_base_vertex_index = element_base;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, element_base, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
}
|
||||
|
||||
// Multidraw Indirect
|
||||
void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
SCOPE_EXIT({
|
||||
// Clean everything.
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
});
|
||||
const u32 start_indirect = parameters[0];
|
||||
const u32 end_indirect = parameters[1];
|
||||
if (start_indirect >= end_indirect) {
|
||||
// Nothing to do.
|
||||
return;
|
||||
}
|
||||
const auto topology =
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[2]);
|
||||
maxwell3d.regs.draw.topology.Assign(topology);
|
||||
const u32 padding = parameters[3];
|
||||
const std::size_t max_draws = parameters[4];
|
||||
|
||||
const u32 indirect_words = 5 + padding;
|
||||
const std::size_t first_draw = start_indirect;
|
||||
const std::size_t effective_draws = end_indirect - start_indirect;
|
||||
const std::size_t last_draw = start_indirect + std::min(effective_draws, max_draws);
|
||||
|
||||
for (std::size_t index = first_draw; index < last_draw; index++) {
|
||||
const std::size_t base = index * indirect_words + 5;
|
||||
const u32 num_vertices = parameters[base];
|
||||
const u32 instance_count = parameters[base + 1];
|
||||
const u32 first_index = parameters[base + 2];
|
||||
const u32 base_vertex = parameters[base + 3];
|
||||
const u32 base_instance = parameters[base + 4];
|
||||
maxwell3d.regs.index_buffer.first = first_index;
|
||||
maxwell3d.regs.vertex_id_base = base_vertex;
|
||||
maxwell3d.regs.index_buffer.count = num_vertices;
|
||||
maxwell3d.regs.global_base_vertex_index = base_vertex;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, base_vertex, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
constexpr std::array<std::pair<u64, HLEFunction>, 4> hle_funcs{{
|
||||
{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
|
||||
{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
|
||||
{0x0217920100488FF7, &HLE_0217920100488FF7},
|
||||
{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
|
||||
}};
|
||||
|
||||
class HLEMacroImpl final : public CachedMacro {
|
||||
public:
|
||||
explicit HLEMacroImpl(Engines::Maxwell3D& maxwell3d_, HLEFunction func_)
|
||||
: maxwell3d{maxwell3d_}, func{func_} {}
|
||||
|
||||
void Execute(const std::vector<u32>& parameters, u32 method) override {
|
||||
func(maxwell3d, parameters);
|
||||
}
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
HLEFunction func;
|
||||
};
|
||||
|
||||
} // Anonymous namespace
|
||||
|
||||
HLEMacro::HLEMacro(Engines::Maxwell3D& maxwell3d_) : maxwell3d{maxwell3d_} {}
|
||||
HLEMacro::~HLEMacro() = default;
|
||||
|
||||
std::unique_ptr<CachedMacro> HLEMacro::GetHLEProgram(u64 hash) const {
|
||||
const auto it = std::find_if(hle_funcs.cbegin(), hle_funcs.cend(),
|
||||
[hash](const auto& pair) { return pair.first == hash; });
|
||||
if (it == hle_funcs.end()) {
|
||||
return nullptr;
|
||||
}
|
||||
return std::make_unique<HLEMacroImpl>(maxwell3d, it->second);
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include <array>
|
||||
#include <vector>
|
||||
#include "common/scope_exit.h"
|
||||
#include "video_core/dirty_flags.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
#include "video_core/macro/macro_hle.h"
|
||||
#include "video_core/rasterizer_interface.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace {
|
||||
|
||||
using HLEFunction = void (*)(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters);
|
||||
|
||||
// HLE'd functions
|
||||
void HLE_771BB18C62444DA0(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = parameters[2] & maxwell3d.GetRegisterValue(0xD1B);
|
||||
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0] & 0x3ffffff));
|
||||
maxwell3d.regs.global_base_instance_index = parameters[5];
|
||||
maxwell3d.regs.global_base_vertex_index = parameters[3];
|
||||
maxwell3d.regs.index_buffer.count = parameters[1];
|
||||
maxwell3d.regs.index_buffer.first = parameters[4];
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
}
|
||||
|
||||
void HLE_0D61FC9FAAC9FCAD(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
|
||||
maxwell3d.regs.vertex_buffer.first = parameters[3];
|
||||
maxwell3d.regs.vertex_buffer.count = parameters[1];
|
||||
maxwell3d.regs.global_base_instance_index = parameters[4];
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(false, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_buffer.count = 0;
|
||||
}
|
||||
|
||||
void HLE_0217920100488FF7(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
const u32 instance_count = (maxwell3d.GetRegisterValue(0xD1B) & parameters[2]);
|
||||
const u32 element_base = parameters[4];
|
||||
const u32 base_instance = parameters[5];
|
||||
maxwell3d.regs.index_buffer.first = parameters[3];
|
||||
maxwell3d.regs.vertex_id_base = element_base;
|
||||
maxwell3d.regs.index_buffer.count = parameters[1];
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.regs.global_base_vertex_index = element_base;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, element_base, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.regs.draw.topology.Assign(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]));
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
}
|
||||
|
||||
// Multidraw Indirect
|
||||
void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
|
||||
SCOPE_EXIT({
|
||||
// Clean everything.
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.regs.index_buffer.count = 0;
|
||||
maxwell3d.regs.global_base_vertex_index = 0x0;
|
||||
maxwell3d.regs.global_base_instance_index = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
});
|
||||
const u32 start_indirect = parameters[0];
|
||||
const u32 end_indirect = parameters[1];
|
||||
if (start_indirect >= end_indirect) {
|
||||
// Nothing to do.
|
||||
return;
|
||||
}
|
||||
const auto topology =
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[2]);
|
||||
maxwell3d.regs.draw.topology.Assign(topology);
|
||||
const u32 padding = parameters[3];
|
||||
const std::size_t max_draws = parameters[4];
|
||||
|
||||
const u32 indirect_words = 5 + padding;
|
||||
const std::size_t first_draw = start_indirect;
|
||||
const std::size_t effective_draws = end_indirect - start_indirect;
|
||||
const std::size_t last_draw = start_indirect + std::min(effective_draws, max_draws);
|
||||
|
||||
for (std::size_t index = first_draw; index < last_draw; index++) {
|
||||
const std::size_t base = index * indirect_words + 5;
|
||||
const u32 num_vertices = parameters[base];
|
||||
const u32 instance_count = parameters[base + 1];
|
||||
const u32 first_index = parameters[base + 2];
|
||||
const u32 base_vertex = parameters[base + 3];
|
||||
const u32 base_instance = parameters[base + 4];
|
||||
maxwell3d.regs.index_buffer.first = first_index;
|
||||
maxwell3d.regs.vertex_id_base = base_vertex;
|
||||
maxwell3d.regs.index_buffer.count = num_vertices;
|
||||
maxwell3d.regs.global_base_vertex_index = base_vertex;
|
||||
maxwell3d.regs.global_base_instance_index = base_instance;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, base_vertex, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
if (maxwell3d.ShouldExecute()) {
|
||||
maxwell3d.Rasterizer().Draw(true, instance_count);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
constexpr std::array<std::pair<u64, HLEFunction>, 4> hle_funcs{{
|
||||
{0x771BB18C62444DA0, &HLE_771BB18C62444DA0},
|
||||
{0x0D61FC9FAAC9FCAD, &HLE_0D61FC9FAAC9FCAD},
|
||||
{0x0217920100488FF7, &HLE_0217920100488FF7},
|
||||
{0x3F5E74B9C9A50164, &HLE_3F5E74B9C9A50164},
|
||||
}};
|
||||
|
||||
class HLEMacroImpl final : public CachedMacro {
|
||||
public:
|
||||
explicit HLEMacroImpl(Engines::Maxwell3D& maxwell3d_, HLEFunction func_)
|
||||
: maxwell3d{maxwell3d_}, func{func_} {}
|
||||
|
||||
void Execute(const std::vector<u32>& parameters, u32 method) override {
|
||||
func(maxwell3d, parameters);
|
||||
}
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
HLEFunction func;
|
||||
};
|
||||
|
||||
} // Anonymous namespace
|
||||
|
||||
HLEMacro::HLEMacro(Engines::Maxwell3D& maxwell3d_) : maxwell3d{maxwell3d_} {}
|
||||
HLEMacro::~HLEMacro() = default;
|
||||
|
||||
std::unique_ptr<CachedMacro> HLEMacro::GetHLEProgram(u64 hash) const {
|
||||
const auto it = std::find_if(hle_funcs.cbegin(), hle_funcs.cend(),
|
||||
[hash](const auto& pair) { return pair.first == hash; });
|
||||
if (it == hle_funcs.end()) {
|
||||
return nullptr;
|
||||
}
|
||||
return std::make_unique<HLEMacroImpl>(maxwell3d, it->second);
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
@@ -1,28 +1,28 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <memory>
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class HLEMacro {
|
||||
public:
|
||||
explicit HLEMacro(Engines::Maxwell3D& maxwell3d_);
|
||||
~HLEMacro();
|
||||
|
||||
// Allocates and returns a cached macro if the hash matches a known function.
|
||||
// Returns nullptr otherwise.
|
||||
[[nodiscard]] std::unique_ptr<CachedMacro> GetHLEProgram(u64 hash) const;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <memory>
|
||||
#include "common/common_types.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class HLEMacro {
|
||||
public:
|
||||
explicit HLEMacro(Engines::Maxwell3D& maxwell3d_);
|
||||
~HLEMacro();
|
||||
|
||||
// Allocates and returns a cached macro if the hash matches a known function.
|
||||
// Returns nullptr otherwise.
|
||||
[[nodiscard]] std::unique_ptr<CachedMacro> GetHLEProgram(u64 hash) const;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
@@ -1,361 +1,361 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include <array>
|
||||
#include <optional>
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/logging/log.h"
|
||||
#include "common/microprofile.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/macro/macro_interpreter.h"
|
||||
|
||||
MICROPROFILE_DEFINE(MacroInterp, "GPU", "Execute macro interpreter", MP_RGB(128, 128, 192));
|
||||
|
||||
namespace Tegra {
|
||||
namespace {
|
||||
class MacroInterpreterImpl final : public CachedMacro {
|
||||
public:
|
||||
explicit MacroInterpreterImpl(Engines::Maxwell3D& maxwell3d_, const std::vector<u32>& code_)
|
||||
: maxwell3d{maxwell3d_}, code{code_} {}
|
||||
|
||||
void Execute(const std::vector<u32>& params, u32 method) override;
|
||||
|
||||
private:
|
||||
/// Resets the execution engine state, zeroing registers, etc.
|
||||
void Reset();
|
||||
|
||||
/**
|
||||
* Executes a single macro instruction located at the current program counter. Returns whether
|
||||
* the interpreter should keep running.
|
||||
*
|
||||
* @param is_delay_slot Whether the current step is being executed due to a delay slot in a
|
||||
* previous instruction.
|
||||
*/
|
||||
bool Step(bool is_delay_slot);
|
||||
|
||||
/// Calculates the result of an ALU operation. src_a OP src_b;
|
||||
u32 GetALUResult(Macro::ALUOperation operation, u32 src_a, u32 src_b);
|
||||
|
||||
/// Performs the result operation on the input result and stores it in the specified register
|
||||
/// (if necessary).
|
||||
void ProcessResult(Macro::ResultOperation operation, u32 reg, u32 result);
|
||||
|
||||
/// Evaluates the branch condition and returns whether the branch should be taken or not.
|
||||
bool EvaluateBranchCondition(Macro::BranchCondition cond, u32 value) const;
|
||||
|
||||
/// Reads an opcode at the current program counter location.
|
||||
Macro::Opcode GetOpcode() const;
|
||||
|
||||
/// Returns the specified register's value. Register 0 is hardcoded to always return 0.
|
||||
u32 GetRegister(u32 register_id) const;
|
||||
|
||||
/// Sets the register to the input value.
|
||||
void SetRegister(u32 register_id, u32 value);
|
||||
|
||||
/// Sets the method address to use for the next Send instruction.
|
||||
void SetMethodAddress(u32 address);
|
||||
|
||||
/// Calls a GPU Engine method with the input parameter.
|
||||
void Send(u32 value);
|
||||
|
||||
/// Reads a GPU register located at the method address.
|
||||
u32 Read(u32 method) const;
|
||||
|
||||
/// Returns the next parameter in the parameter queue.
|
||||
u32 FetchParameter();
|
||||
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
|
||||
/// Current program counter
|
||||
u32 pc{};
|
||||
/// Program counter to execute at after the delay slot is executed.
|
||||
std::optional<u32> delayed_pc;
|
||||
|
||||
/// General purpose macro registers.
|
||||
std::array<u32, Macro::NUM_MACRO_REGISTERS> registers = {};
|
||||
|
||||
/// Method address to use for the next Send instruction.
|
||||
Macro::MethodAddress method_address = {};
|
||||
|
||||
/// Input parameters of the current macro.
|
||||
std::unique_ptr<u32[]> parameters;
|
||||
std::size_t num_parameters = 0;
|
||||
std::size_t parameters_capacity = 0;
|
||||
/// Index of the next parameter that will be fetched by the 'parm' instruction.
|
||||
u32 next_parameter_index = 0;
|
||||
|
||||
bool carry_flag = false;
|
||||
const std::vector<u32>& code;
|
||||
};
|
||||
|
||||
void MacroInterpreterImpl::Execute(const std::vector<u32>& params, u32 method) {
|
||||
MICROPROFILE_SCOPE(MacroInterp);
|
||||
Reset();
|
||||
|
||||
registers[1] = params[0];
|
||||
num_parameters = params.size();
|
||||
|
||||
if (num_parameters > parameters_capacity) {
|
||||
parameters_capacity = num_parameters;
|
||||
parameters = std::make_unique<u32[]>(num_parameters);
|
||||
}
|
||||
std::memcpy(parameters.get(), params.data(), num_parameters * sizeof(u32));
|
||||
|
||||
// Execute the code until we hit an exit condition.
|
||||
bool keep_executing = true;
|
||||
while (keep_executing) {
|
||||
keep_executing = Step(false);
|
||||
}
|
||||
|
||||
// Assert the the macro used all the input parameters
|
||||
ASSERT(next_parameter_index == num_parameters);
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::Reset() {
|
||||
registers = {};
|
||||
pc = 0;
|
||||
delayed_pc = {};
|
||||
method_address.raw = 0;
|
||||
num_parameters = 0;
|
||||
// The next parameter index starts at 1, because $r1 already has the value of the first
|
||||
// parameter.
|
||||
next_parameter_index = 1;
|
||||
carry_flag = false;
|
||||
}
|
||||
|
||||
bool MacroInterpreterImpl::Step(bool is_delay_slot) {
|
||||
u32 base_address = pc;
|
||||
|
||||
Macro::Opcode opcode = GetOpcode();
|
||||
pc += 4;
|
||||
|
||||
// Update the program counter if we were delayed
|
||||
if (delayed_pc) {
|
||||
ASSERT(is_delay_slot);
|
||||
pc = *delayed_pc;
|
||||
delayed_pc = {};
|
||||
}
|
||||
|
||||
switch (opcode.operation) {
|
||||
case Macro::Operation::ALU: {
|
||||
u32 result = GetALUResult(opcode.alu_operation, GetRegister(opcode.src_a),
|
||||
GetRegister(opcode.src_b));
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::AddImmediate: {
|
||||
ProcessResult(opcode.result_operation, opcode.dst,
|
||||
GetRegister(opcode.src_a) + opcode.immediate);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractInsert: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
src = (src >> opcode.bf_src_bit) & opcode.GetBitfieldMask();
|
||||
dst &= ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
|
||||
dst |= src << opcode.bf_dst_bit;
|
||||
ProcessResult(opcode.result_operation, opcode.dst, dst);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractShiftLeftImmediate: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
u32 result = ((src >> dst) & opcode.GetBitfieldMask()) << opcode.bf_dst_bit;
|
||||
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractShiftLeftRegister: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
u32 result = ((src >> opcode.bf_src_bit) & opcode.GetBitfieldMask()) << dst;
|
||||
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::Read: {
|
||||
u32 result = Read(GetRegister(opcode.src_a) + opcode.immediate);
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::Branch: {
|
||||
ASSERT_MSG(!is_delay_slot, "Executing a branch in a delay slot is not valid");
|
||||
u32 value = GetRegister(opcode.src_a);
|
||||
bool taken = EvaluateBranchCondition(opcode.branch_condition, value);
|
||||
if (taken) {
|
||||
// Ignore the delay slot if the branch has the annul bit.
|
||||
if (opcode.branch_annul) {
|
||||
pc = base_address + opcode.GetBranchTarget();
|
||||
return true;
|
||||
}
|
||||
|
||||
delayed_pc = base_address + opcode.GetBranchTarget();
|
||||
// Execute one more instruction due to the delay slot.
|
||||
return Step(true);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented macro operation {}", opcode.operation.Value());
|
||||
}
|
||||
|
||||
// An instruction with the Exit flag will not actually
|
||||
// cause an exit if it's executed inside a delay slot.
|
||||
if (opcode.is_exit && !is_delay_slot) {
|
||||
// Exit has a delay slot, execute the next instruction
|
||||
Step(true);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::GetALUResult(Macro::ALUOperation operation, u32 src_a, u32 src_b) {
|
||||
switch (operation) {
|
||||
case Macro::ALUOperation::Add: {
|
||||
const u64 result{static_cast<u64>(src_a) + src_b};
|
||||
carry_flag = result > 0xffffffff;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::AddWithCarry: {
|
||||
const u64 result{static_cast<u64>(src_a) + src_b + (carry_flag ? 1ULL : 0ULL)};
|
||||
carry_flag = result > 0xffffffff;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::Subtract: {
|
||||
const u64 result{static_cast<u64>(src_a) - src_b};
|
||||
carry_flag = result < 0x100000000;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::SubtractWithBorrow: {
|
||||
const u64 result{static_cast<u64>(src_a) - src_b - (carry_flag ? 0ULL : 1ULL)};
|
||||
carry_flag = result < 0x100000000;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::Xor:
|
||||
return src_a ^ src_b;
|
||||
case Macro::ALUOperation::Or:
|
||||
return src_a | src_b;
|
||||
case Macro::ALUOperation::And:
|
||||
return src_a & src_b;
|
||||
case Macro::ALUOperation::AndNot:
|
||||
return src_a & ~src_b;
|
||||
case Macro::ALUOperation::Nand:
|
||||
return ~(src_a & src_b);
|
||||
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented ALU operation {}", operation);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::ProcessResult(Macro::ResultOperation operation, u32 reg, u32 result) {
|
||||
switch (operation) {
|
||||
case Macro::ResultOperation::IgnoreAndFetch:
|
||||
// Fetch parameter and ignore result.
|
||||
SetRegister(reg, FetchParameter());
|
||||
break;
|
||||
case Macro::ResultOperation::Move:
|
||||
// Move result.
|
||||
SetRegister(reg, result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethod:
|
||||
// Move result and use as Method Address.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
break;
|
||||
case Macro::ResultOperation::FetchAndSend:
|
||||
// Fetch parameter and send result.
|
||||
SetRegister(reg, FetchParameter());
|
||||
Send(result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSend:
|
||||
// Move and send result.
|
||||
SetRegister(reg, result);
|
||||
Send(result);
|
||||
break;
|
||||
case Macro::ResultOperation::FetchAndSetMethod:
|
||||
// Fetch parameter and use result as Method Address.
|
||||
SetRegister(reg, FetchParameter());
|
||||
SetMethodAddress(result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethodFetchAndSend:
|
||||
// Move result and use as Method Address, then fetch and send parameter.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
Send(FetchParameter());
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethodSend:
|
||||
// Move result and use as Method Address, then send bits 12:17 of result.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
Send((result >> 12) & 0b111111);
|
||||
break;
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented result operation {}", operation);
|
||||
}
|
||||
}
|
||||
|
||||
bool MacroInterpreterImpl::EvaluateBranchCondition(Macro::BranchCondition cond, u32 value) const {
|
||||
switch (cond) {
|
||||
case Macro::BranchCondition::Zero:
|
||||
return value == 0;
|
||||
case Macro::BranchCondition::NotZero:
|
||||
return value != 0;
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
Macro::Opcode MacroInterpreterImpl::GetOpcode() const {
|
||||
ASSERT((pc % sizeof(u32)) == 0);
|
||||
ASSERT(pc < code.size() * sizeof(u32));
|
||||
return {code[pc / sizeof(u32)]};
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::GetRegister(u32 register_id) const {
|
||||
return registers.at(register_id);
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::SetRegister(u32 register_id, u32 value) {
|
||||
// Register 0 is hardwired as the zero register.
|
||||
// Ensure no writes to it actually occur.
|
||||
if (register_id == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
registers.at(register_id) = value;
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::SetMethodAddress(u32 address) {
|
||||
method_address.raw = address;
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::Send(u32 value) {
|
||||
maxwell3d.CallMethod(method_address.address, value, true);
|
||||
// Increment the method address by the method increment.
|
||||
method_address.address.Assign(method_address.address.Value() +
|
||||
method_address.increment.Value());
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::Read(u32 method) const {
|
||||
return maxwell3d.GetRegisterValue(method);
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::FetchParameter() {
|
||||
ASSERT(next_parameter_index < num_parameters);
|
||||
return parameters[next_parameter_index++];
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
MacroInterpreter::MacroInterpreter(Engines::Maxwell3D& maxwell3d_)
|
||||
: MacroEngine{maxwell3d_}, maxwell3d{maxwell3d_} {}
|
||||
|
||||
std::unique_ptr<CachedMacro> MacroInterpreter::Compile(const std::vector<u32>& code) {
|
||||
return std::make_unique<MacroInterpreterImpl>(maxwell3d, code);
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include <array>
|
||||
#include <optional>
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/logging/log.h"
|
||||
#include "common/microprofile.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/macro/macro_interpreter.h"
|
||||
|
||||
MICROPROFILE_DEFINE(MacroInterp, "GPU", "Execute macro interpreter", MP_RGB(128, 128, 192));
|
||||
|
||||
namespace Tegra {
|
||||
namespace {
|
||||
class MacroInterpreterImpl final : public CachedMacro {
|
||||
public:
|
||||
explicit MacroInterpreterImpl(Engines::Maxwell3D& maxwell3d_, const std::vector<u32>& code_)
|
||||
: maxwell3d{maxwell3d_}, code{code_} {}
|
||||
|
||||
void Execute(const std::vector<u32>& params, u32 method) override;
|
||||
|
||||
private:
|
||||
/// Resets the execution engine state, zeroing registers, etc.
|
||||
void Reset();
|
||||
|
||||
/**
|
||||
* Executes a single macro instruction located at the current program counter. Returns whether
|
||||
* the interpreter should keep running.
|
||||
*
|
||||
* @param is_delay_slot Whether the current step is being executed due to a delay slot in a
|
||||
* previous instruction.
|
||||
*/
|
||||
bool Step(bool is_delay_slot);
|
||||
|
||||
/// Calculates the result of an ALU operation. src_a OP src_b;
|
||||
u32 GetALUResult(Macro::ALUOperation operation, u32 src_a, u32 src_b);
|
||||
|
||||
/// Performs the result operation on the input result and stores it in the specified register
|
||||
/// (if necessary).
|
||||
void ProcessResult(Macro::ResultOperation operation, u32 reg, u32 result);
|
||||
|
||||
/// Evaluates the branch condition and returns whether the branch should be taken or not.
|
||||
bool EvaluateBranchCondition(Macro::BranchCondition cond, u32 value) const;
|
||||
|
||||
/// Reads an opcode at the current program counter location.
|
||||
Macro::Opcode GetOpcode() const;
|
||||
|
||||
/// Returns the specified register's value. Register 0 is hardcoded to always return 0.
|
||||
u32 GetRegister(u32 register_id) const;
|
||||
|
||||
/// Sets the register to the input value.
|
||||
void SetRegister(u32 register_id, u32 value);
|
||||
|
||||
/// Sets the method address to use for the next Send instruction.
|
||||
void SetMethodAddress(u32 address);
|
||||
|
||||
/// Calls a GPU Engine method with the input parameter.
|
||||
void Send(u32 value);
|
||||
|
||||
/// Reads a GPU register located at the method address.
|
||||
u32 Read(u32 method) const;
|
||||
|
||||
/// Returns the next parameter in the parameter queue.
|
||||
u32 FetchParameter();
|
||||
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
|
||||
/// Current program counter
|
||||
u32 pc{};
|
||||
/// Program counter to execute at after the delay slot is executed.
|
||||
std::optional<u32> delayed_pc;
|
||||
|
||||
/// General purpose macro registers.
|
||||
std::array<u32, Macro::NUM_MACRO_REGISTERS> registers = {};
|
||||
|
||||
/// Method address to use for the next Send instruction.
|
||||
Macro::MethodAddress method_address = {};
|
||||
|
||||
/// Input parameters of the current macro.
|
||||
std::unique_ptr<u32[]> parameters;
|
||||
std::size_t num_parameters = 0;
|
||||
std::size_t parameters_capacity = 0;
|
||||
/// Index of the next parameter that will be fetched by the 'parm' instruction.
|
||||
u32 next_parameter_index = 0;
|
||||
|
||||
bool carry_flag = false;
|
||||
const std::vector<u32>& code;
|
||||
};
|
||||
|
||||
void MacroInterpreterImpl::Execute(const std::vector<u32>& params, u32 method) {
|
||||
MICROPROFILE_SCOPE(MacroInterp);
|
||||
Reset();
|
||||
|
||||
registers[1] = params[0];
|
||||
num_parameters = params.size();
|
||||
|
||||
if (num_parameters > parameters_capacity) {
|
||||
parameters_capacity = num_parameters;
|
||||
parameters = std::make_unique<u32[]>(num_parameters);
|
||||
}
|
||||
std::memcpy(parameters.get(), params.data(), num_parameters * sizeof(u32));
|
||||
|
||||
// Execute the code until we hit an exit condition.
|
||||
bool keep_executing = true;
|
||||
while (keep_executing) {
|
||||
keep_executing = Step(false);
|
||||
}
|
||||
|
||||
// Assert the the macro used all the input parameters
|
||||
ASSERT(next_parameter_index == num_parameters);
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::Reset() {
|
||||
registers = {};
|
||||
pc = 0;
|
||||
delayed_pc = {};
|
||||
method_address.raw = 0;
|
||||
num_parameters = 0;
|
||||
// The next parameter index starts at 1, because $r1 already has the value of the first
|
||||
// parameter.
|
||||
next_parameter_index = 1;
|
||||
carry_flag = false;
|
||||
}
|
||||
|
||||
bool MacroInterpreterImpl::Step(bool is_delay_slot) {
|
||||
u32 base_address = pc;
|
||||
|
||||
Macro::Opcode opcode = GetOpcode();
|
||||
pc += 4;
|
||||
|
||||
// Update the program counter if we were delayed
|
||||
if (delayed_pc) {
|
||||
ASSERT(is_delay_slot);
|
||||
pc = *delayed_pc;
|
||||
delayed_pc = {};
|
||||
}
|
||||
|
||||
switch (opcode.operation) {
|
||||
case Macro::Operation::ALU: {
|
||||
u32 result = GetALUResult(opcode.alu_operation, GetRegister(opcode.src_a),
|
||||
GetRegister(opcode.src_b));
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::AddImmediate: {
|
||||
ProcessResult(opcode.result_operation, opcode.dst,
|
||||
GetRegister(opcode.src_a) + opcode.immediate);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractInsert: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
src = (src >> opcode.bf_src_bit) & opcode.GetBitfieldMask();
|
||||
dst &= ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
|
||||
dst |= src << opcode.bf_dst_bit;
|
||||
ProcessResult(opcode.result_operation, opcode.dst, dst);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractShiftLeftImmediate: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
u32 result = ((src >> dst) & opcode.GetBitfieldMask()) << opcode.bf_dst_bit;
|
||||
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::ExtractShiftLeftRegister: {
|
||||
u32 dst = GetRegister(opcode.src_a);
|
||||
u32 src = GetRegister(opcode.src_b);
|
||||
|
||||
u32 result = ((src >> opcode.bf_src_bit) & opcode.GetBitfieldMask()) << dst;
|
||||
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::Read: {
|
||||
u32 result = Read(GetRegister(opcode.src_a) + opcode.immediate);
|
||||
ProcessResult(opcode.result_operation, opcode.dst, result);
|
||||
break;
|
||||
}
|
||||
case Macro::Operation::Branch: {
|
||||
ASSERT_MSG(!is_delay_slot, "Executing a branch in a delay slot is not valid");
|
||||
u32 value = GetRegister(opcode.src_a);
|
||||
bool taken = EvaluateBranchCondition(opcode.branch_condition, value);
|
||||
if (taken) {
|
||||
// Ignore the delay slot if the branch has the annul bit.
|
||||
if (opcode.branch_annul) {
|
||||
pc = base_address + opcode.GetBranchTarget();
|
||||
return true;
|
||||
}
|
||||
|
||||
delayed_pc = base_address + opcode.GetBranchTarget();
|
||||
// Execute one more instruction due to the delay slot.
|
||||
return Step(true);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented macro operation {}", opcode.operation.Value());
|
||||
}
|
||||
|
||||
// An instruction with the Exit flag will not actually
|
||||
// cause an exit if it's executed inside a delay slot.
|
||||
if (opcode.is_exit && !is_delay_slot) {
|
||||
// Exit has a delay slot, execute the next instruction
|
||||
Step(true);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::GetALUResult(Macro::ALUOperation operation, u32 src_a, u32 src_b) {
|
||||
switch (operation) {
|
||||
case Macro::ALUOperation::Add: {
|
||||
const u64 result{static_cast<u64>(src_a) + src_b};
|
||||
carry_flag = result > 0xffffffff;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::AddWithCarry: {
|
||||
const u64 result{static_cast<u64>(src_a) + src_b + (carry_flag ? 1ULL : 0ULL)};
|
||||
carry_flag = result > 0xffffffff;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::Subtract: {
|
||||
const u64 result{static_cast<u64>(src_a) - src_b};
|
||||
carry_flag = result < 0x100000000;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::SubtractWithBorrow: {
|
||||
const u64 result{static_cast<u64>(src_a) - src_b - (carry_flag ? 0ULL : 1ULL)};
|
||||
carry_flag = result < 0x100000000;
|
||||
return static_cast<u32>(result);
|
||||
}
|
||||
case Macro::ALUOperation::Xor:
|
||||
return src_a ^ src_b;
|
||||
case Macro::ALUOperation::Or:
|
||||
return src_a | src_b;
|
||||
case Macro::ALUOperation::And:
|
||||
return src_a & src_b;
|
||||
case Macro::ALUOperation::AndNot:
|
||||
return src_a & ~src_b;
|
||||
case Macro::ALUOperation::Nand:
|
||||
return ~(src_a & src_b);
|
||||
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented ALU operation {}", operation);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::ProcessResult(Macro::ResultOperation operation, u32 reg, u32 result) {
|
||||
switch (operation) {
|
||||
case Macro::ResultOperation::IgnoreAndFetch:
|
||||
// Fetch parameter and ignore result.
|
||||
SetRegister(reg, FetchParameter());
|
||||
break;
|
||||
case Macro::ResultOperation::Move:
|
||||
// Move result.
|
||||
SetRegister(reg, result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethod:
|
||||
// Move result and use as Method Address.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
break;
|
||||
case Macro::ResultOperation::FetchAndSend:
|
||||
// Fetch parameter and send result.
|
||||
SetRegister(reg, FetchParameter());
|
||||
Send(result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSend:
|
||||
// Move and send result.
|
||||
SetRegister(reg, result);
|
||||
Send(result);
|
||||
break;
|
||||
case Macro::ResultOperation::FetchAndSetMethod:
|
||||
// Fetch parameter and use result as Method Address.
|
||||
SetRegister(reg, FetchParameter());
|
||||
SetMethodAddress(result);
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethodFetchAndSend:
|
||||
// Move result and use as Method Address, then fetch and send parameter.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
Send(FetchParameter());
|
||||
break;
|
||||
case Macro::ResultOperation::MoveAndSetMethodSend:
|
||||
// Move result and use as Method Address, then send bits 12:17 of result.
|
||||
SetRegister(reg, result);
|
||||
SetMethodAddress(result);
|
||||
Send((result >> 12) & 0b111111);
|
||||
break;
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unimplemented result operation {}", operation);
|
||||
}
|
||||
}
|
||||
|
||||
bool MacroInterpreterImpl::EvaluateBranchCondition(Macro::BranchCondition cond, u32 value) const {
|
||||
switch (cond) {
|
||||
case Macro::BranchCondition::Zero:
|
||||
return value == 0;
|
||||
case Macro::BranchCondition::NotZero:
|
||||
return value != 0;
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
Macro::Opcode MacroInterpreterImpl::GetOpcode() const {
|
||||
ASSERT((pc % sizeof(u32)) == 0);
|
||||
ASSERT(pc < code.size() * sizeof(u32));
|
||||
return {code[pc / sizeof(u32)]};
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::GetRegister(u32 register_id) const {
|
||||
return registers.at(register_id);
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::SetRegister(u32 register_id, u32 value) {
|
||||
// Register 0 is hardwired as the zero register.
|
||||
// Ensure no writes to it actually occur.
|
||||
if (register_id == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
registers.at(register_id) = value;
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::SetMethodAddress(u32 address) {
|
||||
method_address.raw = address;
|
||||
}
|
||||
|
||||
void MacroInterpreterImpl::Send(u32 value) {
|
||||
maxwell3d.CallMethod(method_address.address, value, true);
|
||||
// Increment the method address by the method increment.
|
||||
method_address.address.Assign(method_address.address.Value() +
|
||||
method_address.increment.Value());
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::Read(u32 method) const {
|
||||
return maxwell3d.GetRegisterValue(method);
|
||||
}
|
||||
|
||||
u32 MacroInterpreterImpl::FetchParameter() {
|
||||
ASSERT(next_parameter_index < num_parameters);
|
||||
return parameters[next_parameter_index++];
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
MacroInterpreter::MacroInterpreter(Engines::Maxwell3D& maxwell3d_)
|
||||
: MacroEngine{maxwell3d_}, maxwell3d{maxwell3d_} {}
|
||||
|
||||
std::unique_ptr<CachedMacro> MacroInterpreter::Compile(const std::vector<u32>& code) {
|
||||
return std::make_unique<MacroInterpreterImpl>(maxwell3d, code);
|
||||
}
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
@@ -1,27 +1,27 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <vector>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class MacroInterpreter final : public MacroEngine {
|
||||
public:
|
||||
explicit MacroInterpreter(Engines::Maxwell3D& maxwell3d_);
|
||||
|
||||
protected:
|
||||
std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) override;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <vector>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
|
||||
namespace Tegra {
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class MacroInterpreter final : public MacroEngine {
|
||||
public:
|
||||
explicit MacroInterpreter(Engines::Maxwell3D& maxwell3d_);
|
||||
|
||||
protected:
|
||||
std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) override;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,26 +1,26 @@
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class MacroJITx64 final : public MacroEngine {
|
||||
public:
|
||||
explicit MacroJITx64(Engines::Maxwell3D& maxwell3d_);
|
||||
|
||||
protected:
|
||||
std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) override;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/macro/macro.h"
|
||||
|
||||
namespace Tegra {
|
||||
|
||||
namespace Engines {
|
||||
class Maxwell3D;
|
||||
}
|
||||
|
||||
class MacroJITx64 final : public MacroEngine {
|
||||
public:
|
||||
explicit MacroJITx64(Engines::Maxwell3D& maxwell3d_);
|
||||
|
||||
protected:
|
||||
std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) override;
|
||||
|
||||
private:
|
||||
Engines::Maxwell3D& maxwell3d;
|
||||
};
|
||||
|
||||
} // namespace Tegra
|
||||
|
||||
Reference in New Issue
Block a user