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early-access version 1509

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pineappleEA
2021-03-08 07:51:31 +01:00
parent cf27b36f44
commit c3f9e4a27b
3170 changed files with 9341219 additions and 163 deletions
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165
externals/dynarmic/src/frontend/A32/decoder/thumb32.inc vendored
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@@ -29,28 +29,23 @@
//INST(thumb32_LDREXD, "LDREXD", "111010001101------------0111----")
// Data Processing (Shifted Register)
//INST(thumb32_TST_reg, "TST (reg)", "111010100001--------1111--------")
//INST(thumb32_AND_reg, "AND (reg)", "11101010000---------------------")
//INST(thumb32_BIC_reg, "BIC (reg)", "11101010001---------------------")
//INST(thumb32_MOV_reg, "MOV (reg)", "11101010010-1111-000----0000----")
//INST(thumb32_LSL_imm, "LSL (imm)", "11101010010-1111----------00----")
//INST(thumb32_LSR_imm, "LSR (imm)", "11101010010-1111----------01----")
//INST(thumb32_ASR_imm, "ASR (imm)", "11101010010-1111----------10----")
//INST(thumb32_RRX, "RRX", "11101010010-1111-000----0011----")
//INST(thumb32_ROR_imm, "ROR (imm)", "11101010010-1111----------11----")
//INST(thumb32_ORR_reg, "ORR (reg)", "11101010010---------------------")
//INST(thumb32_MVN_reg, "MVN (reg)", "11101010011-1111----------------")
//INST(thumb32_ORN_reg, "ORN (reg)", "11101010011---------------------")
//INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001--------1111--------")
//INST(thumb32_EOR_reg, "EOR (reg)", "11101010100---------------------")
//INST(thumb32_PKH, "PKH", "11101010110---------------------")
//INST(thumb32_CMN_reg, "CMN (reg)", "111010110001--------1111--------")
//INST(thumb32_ADD_reg, "ADD (reg)", "11101011000---------------------")
//INST(thumb32_ADC_reg, "ADC (reg)", "11101011010---------------------")
//INST(thumb32_SBC_reg, "SBC (reg)", "11101011011---------------------")
//INST(thumb32_CMP_reg, "CMP (reg)", "111010111011--------1111--------")
//INST(thumb32_SUB_reg, "SUB (reg)", "11101011101---------------------")
//INST(thumb32_RSB_reg, "RSB (reg)", "11101011110---------------------")
INST(thumb32_TST_reg, "TST (reg)", "111010100001nnnn0vvv1111vvttmmmm")
INST(thumb32_AND_reg, "AND (reg)", "11101010000Snnnn0vvvddddvvttmmmm")
INST(thumb32_BIC_reg, "BIC (reg)", "11101010001Snnnn0vvvddddvvttmmmm")
INST(thumb32_MOV_reg, "MOV (reg)", "11101010010S11110vvvddddvvttmmmm")
INST(thumb32_ORR_reg, "ORR (reg)", "11101010010Snnnn0vvvddddvvttmmmm")
INST(thumb32_MVN_reg, "MVN (reg)", "11101010011S11110vvvddddvvttmmmm")
INST(thumb32_ORN_reg, "ORN (reg)", "11101010011Snnnn0vvvddddvvttmmmm")
INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001nnnn0vvv1111vvttmmmm")
INST(thumb32_EOR_reg, "EOR (reg)", "11101010100Snnnn0vvvddddvvttmmmm")
INST(thumb32_PKH, "PKH", "111010101100nnnn0vvvddddvvt0mmmm")
INST(thumb32_CMN_reg, "CMN (reg)", "111010110001nnnn0vvv1111vvttmmmm")
INST(thumb32_ADD_reg, "ADD (reg)", "11101011000Snnnn0vvvddddvvttmmmm")
INST(thumb32_ADC_reg, "ADC (reg)", "11101011010Snnnn0vvvddddvvttmmmm")
INST(thumb32_SBC_reg, "SBC (reg)", "11101011011Snnnn0vvvddddvvttmmmm")
INST(thumb32_CMP_reg, "CMP (reg)", "111010111011nnnn0vvv1111vvttmmmm")
INST(thumb32_SUB_reg, "SUB (reg)", "11101011101Snnnn0vvvddddvvttmmmm")
INST(thumb32_RSB_reg, "RSB (reg)", "11101011110Snnnn0vvvddddvvttmmmm")
// Data Processing (Modified Immediate)
INST(thumb32_TST_imm, "TST (imm)", "11110v000001nnnn0vvv1111vvvvvvvv")
@@ -58,35 +53,34 @@ INST(thumb32_AND_imm, "AND (imm)", "11110v00000Snnnn0vvvdd
INST(thumb32_BIC_imm, "BIC (imm)", "11110v00001Snnnn0vvvddddvvvvvvvv")
INST(thumb32_MOV_imm, "MOV (imm)", "11110v00010S11110vvvddddvvvvvvvv")
INST(thumb32_ORR_imm, "ORR (imm)", "11110v00010Snnnn0vvvddddvvvvvvvv")
//INST(thumb32_MVN_imm, "MVN (imm)", "11110000011-11110---------------")
//INST(thumb32_ORN_imm, "ORN (imm)", "11110-00011-----0---------------")
//INST(thumb32_TEQ_imm, "TEQ (imm)", "11110-001001----0---1111--------")
//INST(thumb32_EOR_imm, "EOR (imm)", "11110-00100-----0---------------")
//INST(thumb32_CMN_imm, "CMN (imm)", "11110-010001----0---1111--------")
//INST(thumb32_ADD_imm_1, "ADD (imm)", "11110-01000-----0---------------")
//INST(thumb32_ADC_imm, "ADC (imm)", "11110-01010-----0---------------")
//INST(thumb32_SBC_imm, "SBC (imm)", "11110-01011-----0---------------")
//INST(thumb32_CMP_imm, "CMP (imm)", "11110-011011----0---1111--------")
//INST(thumb32_SUB_imm_1, "SUB (imm)", "11110-01101-----0---------------")
//INST(thumb32_RSB_imm, "RSB (imm)", "11110-01110-----0---------------")
INST(thumb32_MVN_imm, "MVN (imm)", "11110v00011S11110vvvddddvvvvvvvv")
INST(thumb32_ORN_imm, "ORN (imm)", "11110v00011Snnnn0vvvddddvvvvvvvv")
INST(thumb32_TEQ_imm, "TEQ (imm)", "11110v001001nnnn0vvv1111vvvvvvvv")
INST(thumb32_EOR_imm, "EOR (imm)", "11110v00100Snnnn0vvvddddvvvvvvvv")
INST(thumb32_CMN_imm, "CMN (imm)", "11110v010001nnnn0vvv1111vvvvvvvv")
INST(thumb32_ADD_imm_1, "ADD (imm)", "11110v01000Snnnn0vvvddddvvvvvvvv")
INST(thumb32_ADC_imm, "ADC (imm)", "11110v01010Snnnn0vvvddddvvvvvvvv")
INST(thumb32_SBC_imm, "SBC (imm)", "11110v01011Snnnn0vvvddddvvvvvvvv")
INST(thumb32_CMP_imm, "CMP (imm)", "11110v011011nnnn0vvv1111vvvvvvvv")
INST(thumb32_SUB_imm_1, "SUB (imm)", "11110v01101Snnnn0vvvddddvvvvvvvv")
INST(thumb32_RSB_imm, "RSB (imm)", "11110v01110Snnnn0vvvddddvvvvvvvv")
// Data Processing (Plain Binary Immediate)
//INST(thumb32_ADR, "ADR", "11110-10000011110---------------")
//INST(thumb32_ADD_imm_2, "ADD (imm)", "11110-100000----0---------------")
//INST(thumb32_MOVW_imm, "MOVW (imm)", "11110-100100----0---------------")
INST(thumb32_ADD_imm_2, "ADD (imm)", "11110i10000011010iiiddddiiiiiiii")
INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii")
//INST(thumb32_ADR, "ADR", "11110-10101011110---------------")
//INST(thumb32_SUB_imm_2, "SUB (imm)", "11110-101010----0---------------")
//INST(thumb32_MOVT, "MOVT", "11110-101100----0---------------")
//INST(thumb32_SSAT, "SSAT", "11110-110000----0---------------")
//INST(thumb32_SSAT16, "SSAT16", "11110-110010----0000----00------")
//INST(thumb32_SSAT, "SSAT", "11110-110010----0---------------")
//INST(thumb32_SBFX, "SBFX", "11110-110100----0---------------")
//INST(thumb32_BFC, "BFC", "11110-11011011110---------------")
//INST(thumb32_BFI, "BFI", "11110-110110----0---------------")
//INST(thumb32_USAT, "USAT", "11110-111000----0---------------")
//INST(thumb32_USAT16, "USAT16", "11110-111010----0000----00------")
//INST(thumb32_USAT, "USAT", "11110-111010----0---------------")
//INST(thumb32_UBFX, "UBFX", "11110-111100----0---------------")
INST(thumb32_SUB_imm_2, "SUB (imm)", "11110i10101011010iiiddddiiiiiiii")
INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii")
INST(thumb32_UDF, "Invalid decoding", "11110011-010----0000----0001----")
INST(thumb32_SSAT16, "SSAT16", "111100110010nnnn0000dddd0000iiii")
INST(thumb32_USAT16, "USAT16", "111100111010nnnn0000dddd0000iiii")
INST(thumb32_SSAT, "SSAT", "1111001100s0nnnn0iiiddddii0bbbbb")
INST(thumb32_USAT, "USAT", "1111001110s0nnnn0iiiddddii0bbbbb")
INST(thumb32_SBFX, "SBFX", "111100110100nnnn0iiiddddii0wwwww")
INST(thumb32_BFC, "BFC", "11110011011011110iiiddddii0bbbbb")
INST(thumb32_BFI, "BFI", "111100110110nnnn0iiiddddii0bbbbb")
INST(thumb32_UBFX, "UBFX", "111100111100nnnn0iiiddddii0wwwww")
// Branches and Miscellaneous Control
//INST(thumb32_MSR_banked, "MSR (banked)", "11110011100-----10-0------1-----")
@@ -95,23 +89,23 @@ INST(thumb32_ORR_imm, "ORR (imm)", "11110v00010Snnnn0vvvdd
//INST(thumb32_MSR_reg_3, "MSR (reg)", "111100111000----10-0--1---0-----")
//INST(thumb32_MSR_reg_4, "MSR (reg)", "111100111000----10-0--00--0-----")
//INST(thumb32_NOP, "NOP", "111100111010----10-0-00000000000")
//INST(thumb32_YIELD, "YIELD", "111100111010----10-0-00000000001")
//INST(thumb32_WFE, "WFE", "111100111010----10-0-00000000010")
//INST(thumb32_WFI, "WFI", "111100111010----10-0-00000000011")
//INST(thumb32_SEV, "SEV", "111100111010----10-0-00000000100")
//INST(thumb32_SEVL, "SEVL", "111100111010----10-0-00000000101")
INST(thumb32_NOP, "NOP", "11110011101011111000000000000000")
INST(thumb32_YIELD, "YIELD", "11110011101011111000000000000001")
INST(thumb32_WFE, "WFE", "11110011101011111000000000000010")
INST(thumb32_WFI, "WFI", "11110011101011111000000000000011")
INST(thumb32_SEV, "SEV", "11110011101011111000000000000100")
INST(thumb32_SEVL, "SEVL", "11110011101011111000000000000101")
//INST(thumb32_DBG, "DBG", "111100111010----10-0-0001111----")
//INST(thumb32_CPS, "CPS", "111100111010----10-0------------")
//INST(thumb32_ENTERX, "ENTERX", "111100111011----10-0----0001----")
//INST(thumb32_LEAVEX, "LEAVEX", "111100111011----10-0----0000----")
//INST(thumb32_CLREX, "CLREX", "111100111011----10-0----0010----")
//INST(thumb32_DSB, "DSB", "111100111011----10-0----0100----")
//INST(thumb32_DMB, "DMB", "111100111011----10-0----0101----")
//INST(thumb32_ISB, "ISB", "111100111011----10-0----0110----")
INST(thumb32_CLREX, "CLREX", "11110011101111111000111100101111")
INST(thumb32_DSB, "DSB", "1111001110111111100011110100oooo")
INST(thumb32_DMB, "DMB", "1111001110111111100011110101oooo")
INST(thumb32_ISB, "ISB", "1111001110111111100011110110oooo")
//INST(thumb32_BXJ, "BXJ", "111100111100----1000111100000000")
INST(thumb32_BXJ, "BXJ", "111100111100mmmm1000111100000000")
//INST(thumb32_ERET, "ERET", "11110011110111101000111100000000")
//INST(thumb32_SUBS_pc_lr, "SUBS PC, LR", "111100111101111010001111--------")
@@ -125,45 +119,46 @@ INST(thumb32_UDF, "UDF", "111101111111----1010--
// Branch instructions
INST(thumb32_BL_imm, "BL (imm)", "11110Svvvvvvvvvv11j1jvvvvvvvvvvv") // v4T
INST(thumb32_BLX_imm, "BLX (imm)", "11110Svvvvvvvvvv11j0jvvvvvvvvvvv") // v5T
//INST(thumb32_B, "B", "11110-----------10-1------------")
//INST(thumb32_B_cond, "B (cond)", "11110-----------10-0------------")
INST(thumb32_B, "B", "11110Svvvvvvvvvv10j1jvvvvvvvvvvv")
INST(thumb32_UDF, "Invalid decoding", "11110-111-------10-0------------")
INST(thumb32_B_cond, "B (cond)", "11110Sccccvvvvvv10i0ivvvvvvvvvvv")
// Store Single Data Item
//INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000--------1--1--------")
//INST(thumb32_STRB_imm_2, "STRB (imm)", "111110000000--------1100--------")
//INST(thumb32_STRB_imm_3, "STRB (imm)", "111110001000--------------------")
//INST(thumb32_STRBT, "STRBT", "111110000000--------1110--------")
//INST(thumb32_STRB, "STRB (reg)", "111110000000--------000000------")
INST(thumb32_STRB, "STRB (reg)", "111110000000nnnntttt000000iimmmm")
//INST(thumb32_STRH_imm_1, "STRH (imm)", "111110000010--------1--1--------")
//INST(thumb32_STRH_imm_2, "STRH (imm)", "111110000010--------1100--------")
//INST(thumb32_STRH_imm_3, "STRH (imm)", "111110001010--------------------")
//INST(thumb32_STRHT, "STRHT", "111110000010--------1110--------")
//INST(thumb32_STRH, "STRH (reg)", "111110000010--------000000------")
INST(thumb32_STRH, "STRH (reg)", "111110000010nnnntttt000000iimmmm")
//INST(thumb32_STR_imm_1, "STR (imm)", "111110000100--------1--1--------")
//INST(thumb32_STR_imm_2, "STR (imm)", "111110000100--------1100--------")
//INST(thumb32_STR_imm_3, "STR (imm)", "111110001100--------------------")
//INST(thumb32_STRT, "STRT", "111110000100--------1110--------")
//INST(thumb32_STR_reg, "STR (reg)", "111110000100--------000000------")
INST(thumb32_STR_reg, "STR (reg)", "111110000100nnnntttt000000iimmmm")
// Load Byte and Memory Hints
//INST(thumb32_PLD_lit, "PLD (lit)", "11111000-00111111111------------")
//INST(thumb32_PLD_reg, "PLD (reg)", "111110000001----1111000000------")
//INST(thumb32_PLD_imm8, "PLD (imm8)", "1111100000-1----11111100--------")
//INST(thumb32_PLD_imm12, "PLD (imm12)", "111110001001----1111------------")
//INST(thumb32_PLI_lit, "PLI (lit)", "11111001-00111111111------------")
//INST(thumb32_PLI_reg, "PLI (reg)", "111110010001----1111000000------")
//INST(thumb32_PLI_imm8, "PLI (imm8)", "111110010001----11111100--------")
//INST(thumb32_PLI_imm12, "PLI (imm12)", "111110011001----1111------------")
//INST(thumb32_LDRB_lit, "LDRB (lit)", "11111000-0011111----------------")
//INST(thumb32_LDRB_reg, "LDRB (reg)", "111110000001--------000000------")
//INST(thumb32_LDRBT, "LDRBT", "111110000001--------1110--------")
//INST(thumb32_LDRB_imm8, "LDRB (imm8)", "111110000001--------1-----------")
//INST(thumb32_LDRB_imm12, "LDRB (imm12)", "111110001001--------------------")
//INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001-0011111----------------")
//INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001--------000000------")
//INST(thumb32_LDRSBT, "LDRSBT", "111110010001--------1110--------")
//INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001--------1-----------")
//INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001--------------------")
INST(thumb32_PLD_lit, "PLD (lit)", "11111000U00111111111iiiiiiiiiiii")
INST(thumb32_PLD_reg, "PLD (reg)", "1111100000W1nnnn1111000000iimmmm")
INST(thumb32_PLD_imm8, "PLD (imm8)", "1111100000W1nnnn11111100iiiiiiii")
INST(thumb32_PLD_imm12, "PLD (imm12)", "1111100010W1nnnn1111iiiiiiiiiiii")
INST(thumb32_PLI_lit, "PLI (lit)", "11111001U00111111111iiiiiiiiiiii")
INST(thumb32_PLI_reg, "PLI (reg)", "111110010001nnnn1111000000iimmmm")
INST(thumb32_PLI_imm8, "PLI (imm8)", "111110010001nnnn11111100iiiiiiii")
INST(thumb32_PLI_imm12, "PLI (imm12)", "111110011001nnnn1111iiiiiiiiiiii")
INST(thumb32_LDRB_lit, "LDRB (lit)", "11111000U0011111ttttiiiiiiiiiiii")
INST(thumb32_LDRB_reg, "LDRB (reg)", "111110000001nnnntttt000000iimmmm")
INST(thumb32_LDRBT, "LDRBT", "111110000001nnnntttt1110iiiiiiii")
INST(thumb32_LDRB_imm8, "LDRB (imm8)", "111110000001nnnntttt1PUWiiiiiiii")
INST(thumb32_LDRB_imm12, "LDRB (imm12)", "111110001001nnnnttttiiiiiiiiiiii")
INST(thumb32_LDRSB_lit, "LDRSB (lit)", "11111001U0011111ttttiiiiiiiiiiii")
INST(thumb32_LDRSB_reg, "LDRSB (reg)", "111110010001nnnntttt000000iimmmm")
INST(thumb32_LDRSBT, "LDRSBT", "111110010001nnnntttt1110iiiiiiii")
INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001nnnntttt1PUWiiiiiiii")
INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001nnnnttttiiiiiiiiiiii")
// Load Halfword and Memory Hints
//INST(thumb32_LDRH_lit, "LDRH (lit)", "11111000-0111111----------------")
@@ -189,10 +184,10 @@ INST(thumb32_BLX_imm, "BLX (imm)", "11110Svvvvvvvvvv11j0jv
//INST(thumb32_LDR_imm12, "LDR (imm12)", "111110001101--------------------")
// Data Processing (register)
//INST(thumb32_LSL_reg, "LSL (reg)", "11111010000-----1111----0000----")
//INST(thumb32_LSR_reg, "LSR (reg)", "11111010001-----1111----0000----")
//INST(thumb32_ASR_reg, "ASR (reg)", "11111010010-----1111----0000----")
//INST(thumb32_ROR_reg, "ROR (reg)", "11111010011-----1111----0000----")
INST(thumb32_LSL_reg, "LSL (reg)", "111110100000mmmm1111dddd0000ssss")
INST(thumb32_LSR_reg, "LSR (reg)", "111110100010mmmm1111dddd0000ssss")
INST(thumb32_ASR_reg, "ASR (reg)", "111110100100mmmm1111dddd0000ssss")
INST(thumb32_ROR_reg, "ROR (reg)", "111110100110mmmm1111dddd0000ssss")
INST(thumb32_SXTH, "SXTH", "11111010000011111111dddd10rrmmmm")
INST(thumb32_SXTAH, "SXTAH", "111110100000nnnn1111dddd10rrmmmm")
INST(thumb32_UXTH, "UXTH", "11111010000111111111dddd10rrmmmm")