early-access version 1718

README.md

@@ -1,7 +1,7 @@
 yuzu emulator early access
 =============
 
-This is the source code for early-access 1717.
+This is the source code for early-access 1718.
 
 ## Legal Notice
 

src/core/arm/arm_interface.h

@@ -65,9 +65,6 @@ public:
     /// Step CPU by one instruction
     virtual void Step() = 0;
 
-    /// Exits execution from a callback, the callback must rewind the stack
-    virtual void ExceptionalExit() = 0;
-
     /// Clear all instruction cache
     virtual void ClearInstructionCache() = 0;
 

src/core/arm/dynarmic/arm_dynarmic_32.cpp

@@ -78,7 +78,9 @@ public:
     }
 
     void CallSVC(u32 swi) override {
-        Kernel::Svc::Call(parent.system, swi);
+        parent.svc_called = true;
+        parent.svc_swi = swi;
+        parent.jit->HaltExecution();
     }
 
     void AddTicks(u64 ticks) override {
@@ -187,11 +189,17 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
 }
 
 void ARM_Dynarmic_32::Run() {
-    jit->Run();
-}
-
-void ARM_Dynarmic_32::ExceptionalExit() {
-    jit->ExceptionalExit();
+    while (true) {
+        jit->Run();
+        if (!svc_called) {
+            break;
+        }
+        svc_called = false;
+        Kernel::Svc::Call(system, svc_swi);
+        if (shutdown) {
+            break;
+        }
+    }
 }
 
 void ARM_Dynarmic_32::Step() {
@@ -275,6 +283,7 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
 
 void ARM_Dynarmic_32::PrepareReschedule() {
     jit->HaltExecution();
+    shutdown = true;
 }
 
 void ARM_Dynarmic_32::ClearInstructionCache() {

src/core/arm/dynarmic/arm_dynarmic_32.h

@@ -42,7 +42,6 @@ public:
     u32 GetPSTATE() const override;
     void SetPSTATE(u32 pstate) override;
     void Run() override;
-    void ExceptionalExit() override;
     void Step() override;
     VAddr GetTlsAddress() const override;
     void SetTlsAddress(VAddr address) override;
@@ -82,6 +81,12 @@ private:
     std::size_t core_index;
     DynarmicExclusiveMonitor& exclusive_monitor;
     std::shared_ptr<Dynarmic::A32::Jit> jit;
+
+    // SVC callback
+    u32 svc_swi{};
+    bool svc_called{};
+
+    bool shutdown{};
 };
 
 } // namespace Core

src/core/arm/dynarmic/arm_dynarmic_64.cpp

@@ -102,7 +102,9 @@ public:
     }
 
     void CallSVC(u32 swi) override {
-        Kernel::Svc::Call(parent.system, swi);
+        parent.svc_called = true;
+        parent.svc_swi = swi;
+        parent.jit->HaltExecution();
     }
 
     void AddTicks(u64 ticks) override {
@@ -227,11 +229,17 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
 }
 
 void ARM_Dynarmic_64::Run() {
-    jit->Run();
-}
-
-void ARM_Dynarmic_64::ExceptionalExit() {
-    jit->ExceptionalExit();
+    while (true) {
+        jit->Run();
+        if (!svc_called) {
+            break;
+        }
+        svc_called = false;
+        Kernel::Svc::Call(system, svc_swi);
+        if (shutdown) {
+            break;
+        }
+    }
 }
 
 void ARM_Dynarmic_64::Step() {
@@ -320,6 +328,7 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
 
 void ARM_Dynarmic_64::PrepareReschedule() {
     jit->HaltExecution();
+    shutdown = true;
 }
 
 void ARM_Dynarmic_64::ClearInstructionCache() {

src/core/arm/dynarmic/arm_dynarmic_64.h

@@ -40,7 +40,6 @@ public:
     void SetPSTATE(u32 pstate) override;
     void Run() override;
     void Step() override;
-    void ExceptionalExit() override;
     VAddr GetTlsAddress() const override;
     void SetTlsAddress(VAddr address) override;
     void SetTPIDR_EL0(u64 value) override;
@@ -75,6 +74,12 @@ private:
     DynarmicExclusiveMonitor& exclusive_monitor;
 
     std::shared_ptr<Dynarmic::A64::Jit> jit;
+
+    // SVC callback
+    u32 svc_swi{};
+    bool svc_called{};
+
+    bool shutdown{};
 };
 
 } // namespace Core

src/core/hle/kernel/k_scheduler.cpp

@@ -659,7 +659,6 @@ void KScheduler::Unload(KThread* thread) {
 
     if (thread) {
         if (thread->IsCallingSvc()) {
-            system.ArmInterface(core_id).ExceptionalExit();
             thread->ClearIsCallingSvc();
         }
         if (!thread->IsTerminationRequested()) {

src/video_core/rasterizer_accelerated.cpp

@@ -18,10 +18,10 @@ RasterizerAccelerated::~RasterizerAccelerated() = default;
 void RasterizerAccelerated::UpdatePagesCachedCount(VAddr addr, u64 size, int delta) {
     const auto page_end = Common::DivCeil(addr + size, Core::Memory::PAGE_SIZE);
     for (auto page = addr >> Core::Memory::PAGE_BITS; page != page_end; ++page) {
-        auto& count = cached_pages.at(page >> 3).Count(page);
+        auto& count = cached_pages.at(page >> 2).Count(page);
 
         if (delta > 0) {
-            ASSERT_MSG(count < UINT8_MAX, "Count may overflow!");
+            ASSERT_MSG(count < UINT16_MAX, "Count may overflow!");
         } else if (delta < 0) {
             ASSERT_MSG(count > 0, "Count may underflow!");
         } else {
@@ -29,7 +29,7 @@ void RasterizerAccelerated::UpdatePagesCachedCount(VAddr addr, u64 size, int del
         }
 
         // Adds or subtracts 1, as count is a unsigned 8-bit value
-        count += static_cast<u8>(delta);
+        count += static_cast<u16>(delta);
 
         // Assume delta is either -1 or 1
         if (count == 0) {

src/video_core/rasterizer_accelerated.h

@@ -29,20 +29,20 @@ private:
     public:
         CacheEntry() = default;
 
-        std::atomic_uint8_t& Count(std::size_t page) {
-            return values[page & 7];
+        std::atomic_uint16_t& Count(std::size_t page) {
+            return values[page & 3];
         }
 
-        const std::atomic_uint8_t& Count(std::size_t page) const {
-            return values[page & 7];
+        const std::atomic_uint16_t& Count(std::size_t page) const {
+            return values[page & 3];
         }
 
     private:
-        std::array<std::atomic_uint8_t, 8> values{};
+        std::array<std::atomic_uint16_t, 4> values{};
     };
     static_assert(sizeof(CacheEntry) == 8, "CacheEntry should be 8 bytes!");
 
-    std::array<CacheEntry, 0x800000> cached_pages;
+    std::array<CacheEntry, 0x1000000> cached_pages;
     Core::Memory::Memory& cpu_memory;
 };