early-access version 3290
This commit is contained in:
@@ -51,6 +51,10 @@ void DrawManager::ProcessMethodCall(u32 method, u32 argument) {
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LOG_WARNING(HW_GPU, "(STUBBED) called");
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break;
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}
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case MAXWELL3D_REG_INDEX(draw_texture.src_y0): {
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DrawTexture();
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break;
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}
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default:
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break;
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}
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@@ -179,6 +183,33 @@ void DrawManager::DrawIndexSmall(u32 argument) {
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ProcessDraw(true, 1);
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}
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void DrawManager::DrawTexture() {
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const auto& regs{maxwell3d->regs};
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draw_texture_state.dst_x0 = static_cast<float>(regs.draw_texture.dst_x0) / 4096.f;
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draw_texture_state.dst_y0 = static_cast<float>(regs.draw_texture.dst_y0) / 4096.f;
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const auto dst_width = static_cast<float>(regs.draw_texture.dst_width) / 4096.f;
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const auto dst_height = static_cast<float>(regs.draw_texture.dst_height) / 4096.f;
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const bool lower_left{regs.window_origin.mode !=
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Maxwell3D::Regs::WindowOrigin::Mode::UpperLeft};
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if (lower_left) {
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draw_texture_state.dst_y0 -= dst_height;
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}
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draw_texture_state.dst_x1 = draw_texture_state.dst_x0 + dst_width;
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draw_texture_state.dst_y1 = draw_texture_state.dst_y0 + dst_height;
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draw_texture_state.src_x0 = static_cast<float>(regs.draw_texture.src_x0) / 4096.f;
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draw_texture_state.src_y0 = static_cast<float>(regs.draw_texture.src_y0) / 4096.f;
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draw_texture_state.src_x1 =
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(static_cast<float>(regs.draw_texture.dx_du) / 4294967295.f) * dst_width +
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draw_texture_state.src_x0;
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draw_texture_state.src_y1 =
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(static_cast<float>(regs.draw_texture.dy_dv) / 4294967295.f) * dst_height +
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draw_texture_state.src_y0;
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draw_texture_state.src_sampler = regs.draw_texture.src_sampler;
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draw_texture_state.src_texture = regs.draw_texture.src_texture;
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maxwell3d->rasterizer->DrawTexture();
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}
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void DrawManager::UpdateTopology() {
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const auto& regs{maxwell3d->regs};
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switch (regs.primitive_topology_control) {
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@@ -32,6 +32,19 @@ public:
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std::vector<u8> inline_index_draw_indexes;
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};
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struct DrawTextureState {
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f32 dst_x0;
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f32 dst_y0;
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f32 dst_x1;
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f32 dst_y1;
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f32 src_x0;
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f32 src_y0;
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f32 src_x1;
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f32 src_y1;
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u32 src_sampler;
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u32 src_texture;
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};
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struct IndirectParams {
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bool is_indexed;
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bool include_count;
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@@ -64,6 +77,10 @@ public:
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return draw_state;
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}
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const DrawTextureState& GetDrawTextureState() const {
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return draw_texture_state;
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}
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IndirectParams& GetIndirectParams() {
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return indirect_state;
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}
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@@ -81,6 +98,8 @@ private:
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void DrawIndexSmall(u32 argument);
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void DrawTexture();
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void UpdateTopology();
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void ProcessDraw(bool draw_indexed, u32 instance_count);
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@@ -89,6 +108,7 @@ private:
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Maxwell3D* maxwell3d{};
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State draw_state{};
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DrawTextureState draw_texture_state{};
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IndirectParams indirect_state{};
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};
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} // namespace Tegra::Engines
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@@ -76,7 +76,7 @@ void State::ProcessData(std::span<const u8> read_buffer) {
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regs.dest.height, regs.dest.depth, x_offset, regs.dest.y,
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x_elements, regs.line_count, regs.dest.BlockHeight(),
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regs.dest.BlockDepth(), regs.line_length_in);
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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memory_manager.WriteBlockCached(address, tmp_buffer.data(), dst_size);
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}
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}
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@@ -6,6 +6,7 @@
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#include "common/microprofile.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/sw_blitter/blitter.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/surface.h"
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#include "video_core/textures/decoders.h"
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@@ -20,8 +21,8 @@ namespace Tegra::Engines {
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using namespace Texture;
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Fermi2D::Fermi2D(MemoryManager& memory_manager_) {
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sw_blitter = std::make_unique<Blitter::SoftwareBlitEngine>(memory_manager_);
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Fermi2D::Fermi2D(MemoryManager& memory_manager_) : memory_manager{memory_manager_} {
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sw_blitter = std::make_unique<Blitter::SoftwareBlitEngine>(memory_manager);
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// Nvidia's OpenGL driver seems to assume these values
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regs.src.depth = 1;
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regs.dst.depth = 1;
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@@ -104,6 +105,7 @@ void Fermi2D::Blit() {
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config.src_x0 = 0;
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}
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memory_manager.FlushCaching();
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if (!rasterizer->AccelerateSurfaceCopy(src, regs.dst, config)) {
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sw_blitter->Blit(src, regs.dst, config);
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}
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@@ -305,6 +305,7 @@ public:
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private:
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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std::unique_ptr<Blitter::SoftwareBlitEngine> sw_blitter;
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MemoryManager& memory_manager;
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// registers.
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@@ -149,6 +149,7 @@ bool Maxwell3D::IsMethodExecutable(u32 method) {
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case MAXWELL3D_REG_INDEX(inline_index_4x8.index0):
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case MAXWELL3D_REG_INDEX(vertex_array_instance_first):
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case MAXWELL3D_REG_INDEX(vertex_array_instance_subsequent):
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case MAXWELL3D_REG_INDEX(draw_texture.src_y0):
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case MAXWELL3D_REG_INDEX(wait_for_idle):
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case MAXWELL3D_REG_INDEX(shadow_ram_control):
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case MAXWELL3D_REG_INDEX(load_mme.instruction_ptr):
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@@ -485,11 +486,6 @@ void Maxwell3D::StampQueryResult(u64 payload, bool long_query) {
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}
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void Maxwell3D::ProcessQueryGet() {
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// TODO(Subv): Support the other query units.
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if (regs.report_semaphore.query.location != Regs::ReportSemaphore::Location::All) {
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LOG_DEBUG(HW_GPU, "Locations other than ALL are unimplemented");
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}
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switch (regs.report_semaphore.query.operation) {
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case Regs::ReportSemaphore::Operation::Release:
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if (regs.report_semaphore.query.short_query != 0) {
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@@ -649,7 +645,7 @@ void Maxwell3D::ProcessCBMultiData(const u32* start_base, u32 amount) {
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const GPUVAddr address{buffer_address + regs.const_buffer.offset};
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const size_t copy_size = amount * sizeof(u32);
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memory_manager.WriteBlock(address, start_base, copy_size);
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memory_manager.WriteBlockCached(address, start_base, copy_size);
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// Increment the current buffer position.
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regs.const_buffer.offset += static_cast<u32>(copy_size);
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@@ -1599,6 +1599,20 @@ public:
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};
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static_assert(sizeof(TIRModulationCoeff) == 0x4);
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struct DrawTexture {
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s32 dst_x0;
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s32 dst_y0;
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s32 dst_width;
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s32 dst_height;
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s64 dx_du;
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s64 dy_dv;
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u32 src_sampler;
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u32 src_texture;
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s32 src_x0;
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s32 src_y0;
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};
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static_assert(sizeof(DrawTexture) == 0x30);
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struct ReduceColorThreshold {
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union {
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BitField<0, 8, u32> all_hit_once;
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@@ -2751,7 +2765,7 @@ public:
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u32 reserved_sw_method2; ///< 0x102C
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std::array<TIRModulationCoeff, 5> tir_modulation_coeff; ///< 0x1030
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std::array<u32, 15> spare_nop; ///< 0x1044
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INSERT_PADDING_BYTES_NOINIT(0x30);
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DrawTexture draw_texture; ///< 0x1080
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std::array<u32, 7> reserved_sw_method3_to_7; ///< 0x10B0
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ReduceColorThreshold reduce_color_thresholds_unorm8; ///< 0x10CC
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std::array<u32, 4> reserved_sw_method10_to_13; ///< 0x10D0
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@@ -69,7 +69,7 @@ void MaxwellDMA::Launch() {
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if (launch.multi_line_enable) {
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const bool is_src_pitch = launch.src_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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const bool is_dst_pitch = launch.dst_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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memory_manager.FlushCaching();
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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CopyBlockLinearToBlockLinear();
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@@ -104,6 +104,7 @@ void MaxwellDMA::Launch() {
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reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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} else {
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memory_manager.FlushCaching();
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const auto convert_linear_2_blocklinear_addr = [](u64 address) {
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return (address & ~0x1f0ULL) | ((address & 0x40) >> 2) | ((address & 0x10) << 1) |
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((address & 0x180) >> 1) | ((address & 0x20) << 3);
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@@ -121,8 +122,8 @@ void MaxwellDMA::Launch() {
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memory_manager.ReadBlockUnsafe(
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convert_linear_2_blocklinear_addr(regs.offset_in + offset),
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tmp_buffer.data(), tmp_buffer.size());
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memory_manager.WriteBlock(regs.offset_out + offset, tmp_buffer.data(),
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tmp_buffer.size());
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memory_manager.WriteBlockCached(regs.offset_out + offset, tmp_buffer.data(),
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tmp_buffer.size());
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}
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} else if (is_src_pitch && !is_dst_pitch) {
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UNIMPLEMENTED_IF(regs.line_length_in % 16 != 0);
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@@ -132,7 +133,7 @@ void MaxwellDMA::Launch() {
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for (u32 offset = 0; offset < regs.line_length_in; offset += 16) {
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memory_manager.ReadBlockUnsafe(regs.offset_in + offset, tmp_buffer.data(),
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tmp_buffer.size());
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memory_manager.WriteBlock(
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memory_manager.WriteBlockCached(
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convert_linear_2_blocklinear_addr(regs.offset_out + offset),
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tmp_buffer.data(), tmp_buffer.size());
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}
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@@ -141,8 +142,8 @@ void MaxwellDMA::Launch() {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(),
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regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(),
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regs.line_length_in);
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memory_manager.WriteBlockCached(regs.offset_out, tmp_buffer.data(),
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regs.line_length_in);
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}
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}
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}
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@@ -204,7 +205,7 @@ void MaxwellDMA::CopyBlockLinearToPitch() {
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src_params.origin.y, x_elements, regs.line_count, block_height, block_depth,
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regs.pitch_out);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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memory_manager.WriteBlockCached(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::CopyPitchToBlockLinear() {
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@@ -256,7 +257,7 @@ void MaxwellDMA::CopyPitchToBlockLinear() {
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dst_params.origin.y, x_elements, regs.line_count, block_height, block_depth,
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regs.pitch_in);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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memory_manager.WriteBlockCached(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::FastCopyBlockLinearToPitch() {
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@@ -287,7 +288,7 @@ void MaxwellDMA::FastCopyBlockLinearToPitch() {
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regs.src_params.block_size.height, regs.src_params.block_size.depth,
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regs.pitch_out);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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memory_manager.WriteBlockCached(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::CopyBlockLinearToBlockLinear() {
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@@ -347,7 +348,7 @@ void MaxwellDMA::CopyBlockLinearToBlockLinear() {
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dst.depth, dst_x_offset, dst.origin.y, x_elements, regs.line_count,
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dst.block_size.height, dst.block_size.depth, pitch);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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memory_manager.WriteBlockCached(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::ReleaseSemaphore() {
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