early-access version 1870

src/shader_recompiler/backend/glasm/emit_context.h

@@ -59,7 +59,7 @@ public:
     }
 
     std::string code;
-    RegAlloc reg_alloc{*this};
+    RegAlloc reg_alloc{};
     const Info& info;
     const Profile& profile;
     const RuntimeInfo& runtime_info;

src/shader_recompiler/backend/glasm/emit_glasm.cpp

@@ -2,7 +2,7 @@
 // Licensed under GPLv2 or any later version
 // Refer to the license.txt file included.
 
-#include <ranges>
+#include <algorithm>
 #include <string>
 #include <tuple>
 
@@ -196,7 +196,10 @@ void PrecolorInst(IR::Inst& phi) {
 
 void Precolor(const IR::Program& program) {
     for (IR::Block* const block : program.blocks) {
-        for (IR::Inst& phi : block->Instructions() | std::views::take_while(IR::IsPhi)) {
+        for (IR::Inst& phi : block->Instructions()) {
+            if (!IR::IsPhi(phi)) {
+                break;
+            }
             PrecolorInst(phi);
         }
     }

src/shader_recompiler/backend/glasm/reg_alloc.h

@@ -86,7 +86,7 @@ struct ScalarF64 : Value {};
 
 class RegAlloc {
 public:
-    RegAlloc(EmitContext& ctx_) : ctx{ctx_} {}
+    RegAlloc() = default;
 
     Register Define(IR::Inst& inst);
 
@@ -142,7 +142,6 @@ private:
 
     void Free(Id id);
 
-    EmitContext& ctx;
     size_t num_used_registers{};
     size_t num_used_long_registers{};
     std::bitset<NUM_REGS> register_use{};

src/shader_recompiler/backend/glsl/emit_glsl.cpp

@@ -2,8 +2,10 @@
 // Licensed under GPLv2 or any later version
 // Refer to the license.txt file included.
 
-#include <ranges>
+#include <algorithm>
 #include <string>
+#include <tuple>
+#include <type_traits>
 
 #include "common/div_ceil.h"
 #include "common/settings.h"
@@ -120,7 +122,10 @@ void PrecolorInst(IR::Inst& phi) {
 
 void Precolor(const IR::Program& program) {
     for (IR::Block* const block : program.blocks) {
-        for (IR::Inst& phi : block->Instructions() | std::views::take_while(IR::IsPhi)) {
+        for (IR::Inst& phi : block->Instructions()) {
+            if (!IR::IsPhi(phi)) {
+                break;
+            }
             PrecolorInst(phi);
         }
     }
@@ -218,8 +223,15 @@ std::string EmitGLSL(const Profile& profile, const RuntimeInfo& runtime_info, IR
     const std::string version{fmt::format("#version 450{}\n", GlslVersionSpecifier(ctx))};
     ctx.header.insert(0, version);
     if (program.shared_memory_size > 0) {
-        ctx.header +=
-            fmt::format("shared uint smem[{}];", Common::DivCeil(program.shared_memory_size, 4U));
+        const auto requested_size{program.shared_memory_size};
+        const auto max_size{profile.gl_max_compute_smem_size};
+        const bool needs_clamp{requested_size > max_size};
+        if (needs_clamp) {
+            LOG_WARNING(Shader_GLSL, "Requested shared memory size ({}) exceeds device limit ({})",
+                        requested_size, max_size);
+        }
+        const auto smem_size{needs_clamp ? max_size : requested_size};
+        ctx.header += fmt::format("shared uint smem[{}];", Common::DivCeil(smem_size, 4U));
     }
     ctx.header += "void main(){\n";
     if (program.local_memory_size > 0) {

src/shader_recompiler/backend/glsl/emit_glsl_floating_point.cpp

@@ -22,7 +22,7 @@ void Compare(EmitContext& ctx, IR::Inst& inst, std::string_view lhs, std::string
 }
 
 bool IsPrecise(const IR::Inst& inst) {
-    return {inst.Flags<IR::FpControl>().no_contraction};
+    return inst.Flags<IR::FpControl>().no_contraction;
 }
 } // Anonymous namespace
 

src/shader_recompiler/backend/spirv/emit_spirv_image.cpp

@@ -109,7 +109,7 @@ private:
             return;
         }
         if (offset.IsImmediate()) {
-            Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(offset.U32()));
+            Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(static_cast<s32>(offset.U32())));
             return;
         }
         IR::Inst* const inst{offset.InstRecursive()};
@@ -117,16 +117,21 @@ private:
             switch (inst->GetOpcode()) {
             case IR::Opcode::CompositeConstructU32x2:
                 Add(spv::ImageOperandsMask::ConstOffset,
-                    ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32()));
+                    ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
+                               static_cast<s32>(inst->Arg(1).U32())));
                 return;
             case IR::Opcode::CompositeConstructU32x3:
                 Add(spv::ImageOperandsMask::ConstOffset,
-                    ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32()));
+                    ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
+                               static_cast<s32>(inst->Arg(1).U32()),
+                               static_cast<s32>(inst->Arg(2).U32())));
                 return;
             case IR::Opcode::CompositeConstructU32x4:
                 Add(spv::ImageOperandsMask::ConstOffset,
-                    ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32(),
-                               inst->Arg(3).U32()));
+                    ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
+                               static_cast<s32>(inst->Arg(1).U32()),
+                               static_cast<s32>(inst->Arg(2).U32()),
+                               static_cast<s32>(inst->Arg(3).U32())));
                 return;
             default:
                 break;