98 lines
4.4 KiB
C++
Executable File
98 lines
4.4 KiB
C++
Executable File
// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra::Host1x::NvdecCommon {
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enum class VideoCodec : u64 {
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None = 0x0,
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H264 = 0x3,
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VP8 = 0x5,
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H265 = 0x7,
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VP9 = 0x9,
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};
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// NVDEC should use a 32-bit address space, but is mapped to 64-bit,
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// doubling the sizes here is compensating for that.
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struct NvdecRegisters {
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static constexpr std::size_t NUM_REGS = 0x178;
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union {
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struct {
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INSERT_PADDING_WORDS_NOINIT(256); ///< 0x0000
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VideoCodec set_codec_id; ///< 0x0400
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INSERT_PADDING_WORDS_NOINIT(126); ///< 0x0408
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u64 execute; ///< 0x0600
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INSERT_PADDING_WORDS_NOINIT(126); ///< 0x0608
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struct { ///< 0x0800
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union {
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BitField<0, 3, VideoCodec> codec;
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BitField<4, 1, u64> gp_timer_on;
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BitField<13, 1, u64> mb_timer_on;
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BitField<14, 1, u64> intra_frame_pslc;
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BitField<17, 1, u64> all_intra_frame;
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};
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} control_params;
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u64 picture_info_offset; ///< 0x0808
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u64 frame_bitstream_offset; ///< 0x0810
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u64 frame_number; ///< 0x0818
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u64 h264_slice_data_offsets; ///< 0x0820
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u64 h264_mv_dump_offset; ///< 0x0828
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INSERT_PADDING_WORDS_NOINIT(6); ///< 0x0830
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u64 frame_stats_offset; ///< 0x0848
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u64 h264_last_surface_luma_offset; ///< 0x0850
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u64 h264_last_surface_chroma_offset; ///< 0x0858
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std::array<u64, 17> surface_luma_offset; ///< 0x0860
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std::array<u64, 17> surface_chroma_offset; ///< 0x08E8
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INSERT_PADDING_WORDS_NOINIT(68); ///< 0x0970
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u64 vp8_prob_data_offset; ///< 0x0A80
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u64 vp8_header_partition_buf_offset; ///< 0x0A88
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INSERT_PADDING_WORDS_NOINIT(60); ///< 0x0A90
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u64 vp9_entropy_probs_offset; ///< 0x0B80
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u64 vp9_backward_updates_offset; ///< 0x0B88
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u64 vp9_last_frame_segmap_offset; ///< 0x0B90
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u64 vp9_curr_frame_segmap_offset; ///< 0x0B98
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INSERT_PADDING_WORDS_NOINIT(2); ///< 0x0BA0
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u64 vp9_last_frame_mvs_offset; ///< 0x0BA8
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u64 vp9_curr_frame_mvs_offset; ///< 0x0BB0
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INSERT_PADDING_WORDS_NOINIT(2); ///< 0x0BB8
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};
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std::array<u64, NUM_REGS> reg_array;
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};
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};
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static_assert(sizeof(NvdecRegisters) == (0xBC0), "NvdecRegisters is incorrect size");
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(NvdecRegisters, field_name) == position * sizeof(u64), \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(set_codec_id, 0x80);
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ASSERT_REG_POSITION(execute, 0xC0);
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ASSERT_REG_POSITION(control_params, 0x100);
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ASSERT_REG_POSITION(picture_info_offset, 0x101);
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ASSERT_REG_POSITION(frame_bitstream_offset, 0x102);
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ASSERT_REG_POSITION(frame_number, 0x103);
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ASSERT_REG_POSITION(h264_slice_data_offsets, 0x104);
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ASSERT_REG_POSITION(frame_stats_offset, 0x109);
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ASSERT_REG_POSITION(h264_last_surface_luma_offset, 0x10A);
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ASSERT_REG_POSITION(h264_last_surface_chroma_offset, 0x10B);
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ASSERT_REG_POSITION(surface_luma_offset, 0x10C);
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ASSERT_REG_POSITION(surface_chroma_offset, 0x11D);
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ASSERT_REG_POSITION(vp8_prob_data_offset, 0x150);
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ASSERT_REG_POSITION(vp8_header_partition_buf_offset, 0x151);
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ASSERT_REG_POSITION(vp9_entropy_probs_offset, 0x170);
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ASSERT_REG_POSITION(vp9_backward_updates_offset, 0x171);
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ASSERT_REG_POSITION(vp9_last_frame_segmap_offset, 0x172);
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ASSERT_REG_POSITION(vp9_curr_frame_segmap_offset, 0x173);
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ASSERT_REG_POSITION(vp9_last_frame_mvs_offset, 0x175);
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ASSERT_REG_POSITION(vp9_curr_frame_mvs_offset, 0x176);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Host1x::NvdecCommon
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