137 lines
3.3 KiB
C++
Executable File
137 lines
3.3 KiB
C++
Executable File
// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <vector>
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#include <queue>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "video_core/command_classes/sync_manager.h"
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namespace Tegra {
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class GPU;
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class Nvdec;
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class Vic;
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class Host1x;
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enum class ChSubmissionMode : u32 {
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SetClass = 0,
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Incrementing = 1,
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NonIncrementing = 2,
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Mask = 3,
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Immediate = 4,
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Restart = 5,
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Gather = 6,
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};
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enum class ChClassId : u32 {
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NoClass = 0x0,
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Host1x = 0x1,
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VideoEncodeMpeg = 0x20,
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VideoEncodeNvEnc = 0x21,
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VideoStreamingVi = 0x30,
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VideoStreamingIsp = 0x32,
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VideoStreamingIspB = 0x34,
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VideoStreamingViI2c = 0x36,
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GraphicsVic = 0x5d,
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Graphics3D = 0x60,
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GraphicsGpu = 0x61,
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Tsec = 0xe0,
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TsecB = 0xe1,
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NvJpg = 0xc0,
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NvDec = 0xf0
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};
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enum class ChMethod : u32 {
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Empty = 0,
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SetMethod = 0x10,
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SetData = 0x11,
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};
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union ChCommandHeader {
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u32 raw;
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BitField<0, 16, u32> value;
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BitField<16, 12, ChMethod> method_offset;
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BitField<28, 4, ChSubmissionMode> submission_mode;
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};
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static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
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struct ChCommand {
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ChClassId class_id{};
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int method_offset{};
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std::vector<u32> arguments;
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};
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using ChCommandHeaderList = std::vector<ChCommandHeader>;
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using ChCommandList = std::vector<ChCommand>;
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struct ThiRegisters {
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u32_le increment_syncpt{};
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INSERT_PADDING_WORDS(1);
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u32_le increment_syncpt_error{};
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u32_le ctx_switch_incremement_syncpt{};
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INSERT_PADDING_WORDS(4);
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u32_le ctx_switch{};
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INSERT_PADDING_WORDS(1);
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u32_le ctx_syncpt_eof{};
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INSERT_PADDING_WORDS(5);
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u32_le method_0{};
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u32_le method_1{};
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INSERT_PADDING_WORDS(12);
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u32_le int_status{};
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u32_le int_mask{};
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};
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enum class ThiMethod : u32 {
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IncSyncpt = offsetof(ThiRegisters, increment_syncpt) / sizeof(u32),
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SetMethod0 = offsetof(ThiRegisters, method_0) / sizeof(u32),
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SetMethod1 = offsetof(ThiRegisters, method_1) / sizeof(u32),
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};
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class CDmaPusher {
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public:
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explicit CDmaPusher(GPU& gpu_);
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~CDmaPusher();
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/// Push NVDEC command buffer entries into queue
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void Push(ChCommandHeaderList&& entries);
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/// Process queued command buffer entries
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void DispatchCalls();
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/// Process one queue element
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void Step();
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/// Invoke command class devices to execute the command based on the current state
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void ExecuteCommand(u32 state_offset, u32 data);
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private:
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/// Write arguments value to the ThiRegisters member at the specified offset
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void ThiStateWrite(ThiRegisters& state, u32 state_offset, const std::vector<u32>& arguments);
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GPU& gpu;
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std::shared_ptr<Tegra::Nvdec> nvdec_processor;
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std::unique_ptr<Tegra::Vic> vic_processor;
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std::unique_ptr<Tegra::Host1x> host1x_processor;
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std::unique_ptr<SyncptIncrManager> sync_manager;
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ChClassId current_class{};
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ThiRegisters vic_thi_state{};
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ThiRegisters nvdec_thi_state{};
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s32 count{};
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s32 offset{};
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s32 mask{};
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bool incrementing{};
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// Queue of command lists to be processed
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std::queue<ChCommandHeaderList> cdma_queue;
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};
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} // namespace Tegra
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