early-access version 4113
This commit is contained in:
parent
3a104e1343
commit
cd70dbf1d5
@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 4111.
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This is the source code for early-access 4113.
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## Legal Notice
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@ -13,20 +13,101 @@ Scheduler::Scheduler(GPU& gpu_) : gpu{gpu_} {}
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Scheduler::~Scheduler() = default;
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void Scheduler::Init() {
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master_control = Common::Fiber::ThreadToFiber();
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}
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void Scheduler::Resume() {
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bool nothing_pending;
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do {
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nothing_pending = true;
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current_fifo = nullptr;
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{
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std::unique_lock lk(scheduling_guard);
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size_t num_iters = gpfifos.size();
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for (size_t i = 0; i < num_iters; i++) {
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size_t current_id = (current_fifo_rotation_id + i) % gpfifos.size();
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auto& fifo = gpfifos[current_id];
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if (!fifo.is_active) {
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continue;
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}
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std::scoped_lock lk2(fifo.guard);
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if (!fifo.pending_work.empty() || fifo.working.load(std::memory_order_acquire)) {
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current_fifo = &fifo;
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current_fifo_rotation_id = current_id;
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nothing_pending = false;
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break;
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}
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}
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}
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if (current_fifo) {
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Common::Fiber::YieldTo(master_control, *current_fifo->context);
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current_fifo = nullptr;
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}
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} while (!nothing_pending);
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}
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void Scheduler::Yield() {
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ASSERT(current_fifo != nullptr);
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Common::Fiber::YieldTo(current_fifo->context, *master_control);
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}
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void Scheduler::Push(s32 channel, CommandList&& entries) {
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std::unique_lock lk(scheduling_guard);
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auto it = channels.find(channel);
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ASSERT(it != channels.end());
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auto channel_state = it->second;
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gpu.BindChannel(channel_state->bind_id);
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channel_state->dma_pusher->Push(std::move(entries));
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channel_state->dma_pusher->DispatchCalls();
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auto it = channel_gpfifo_ids.find(channel);
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ASSERT(it != channel_gpfifo_ids.end());
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auto gpfifo_id = it->second;
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auto& fifo = gpfifos[gpfifo_id];
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{
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std::scoped_lock lk2(fifo.guard);
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fifo.pending_work.emplace_back(std::move(entries));
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}
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}
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void Scheduler::ChannelLoop(size_t gpfifo_id, s32 channel_id) {
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gpu.BindChannel(channel_id);
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auto& fifo = gpfifos[gpfifo_id];
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while (true) {
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auto* channel_state = channels[channel_id].get();
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fifo.guard.lock();
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while (!fifo.pending_work.empty()) {
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{
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fifo.working.store(true, std::memory_order_release);
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CommandList&& entries = std::move(fifo.pending_work.front());
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channel_state->dma_pusher->Push(std::move(entries));
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fifo.pending_work.pop_front();
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}
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fifo.guard.unlock();
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channel_state->dma_pusher->DispatchCalls();
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fifo.guard.lock();
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}
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fifo.working.store(false, std::memory_order_relaxed);
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fifo.guard.unlock();
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Common::Fiber::YieldTo(fifo.context, *master_control);
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gpu.BindChannel(channel_id);
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}
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}
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void Scheduler::DeclareChannel(std::shared_ptr<ChannelState> new_channel) {
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s32 channel = new_channel->bind_id;
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std::unique_lock lk(scheduling_guard);
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channels.emplace(channel, new_channel);
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size_t new_fifo_id;
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if (!free_fifos.empty()) {
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new_fifo_id = free_fifos.front();
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free_fifos.pop_front();
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} else {
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new_fifo_id = gpfifos.size();
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gpfifos.emplace_back();
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}
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auto& new_fifo = gpfifos[new_fifo_id];
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channel_gpfifo_ids[channel] = new_fifo_id;
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new_fifo.is_active = true;
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new_fifo.bind_id = channel;
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new_fifo.pending_work.clear();
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std::function<void()> callback = std::bind(&Scheduler::ChannelLoop, this, new_fifo_id, channel);
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new_fifo.context = std::make_shared<Common::Fiber>(std::move(callback));
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}
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} // namespace Tegra::Control
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@ -3,10 +3,13 @@
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#pragma once
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#include <atomic>
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#include <deque>
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#include <memory>
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#include <mutex>
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#include <unordered_map>
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#include "common/fiber.h"
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#include "video_core/dma_pusher.h"
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namespace Tegra {
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@ -22,14 +25,36 @@ public:
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explicit Scheduler(GPU& gpu_);
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~Scheduler();
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void Init();
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void Resume();
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void Yield();
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void Push(s32 channel, CommandList&& entries);
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void DeclareChannel(std::shared_ptr<ChannelState> new_channel);
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private:
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void ChannelLoop(size_t gpfifo_id, s32 channel_id);
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std::unordered_map<s32, std::shared_ptr<ChannelState>> channels;
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std::unordered_map<s32, size_t> channel_gpfifo_ids;
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std::mutex scheduling_guard;
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std::shared_ptr<Common::Fiber> master_control;
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struct GPFifoContext {
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bool is_active;
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std::shared_ptr<Common::Fiber> context;
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std::deque<CommandList> pending_work;
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std::atomic<bool> working{};
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std::mutex guard;
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s32 bind_id;
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};
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std::deque<GPFifoContext> gpfifos;
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std::deque<size_t> free_fifos;
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GPU& gpu;
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size_t current_fifo_rotation_id{};
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GPFifoContext* current_fifo{};
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};
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} // namespace Control
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@ -6,6 +6,7 @@
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#include "common/settings.h"
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#include "core/core.h"
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#include "video_core/control/channel_state.h"
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#include "video_core/control/scheduler.h"
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#include "video_core/dma_pusher.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_compute.h"
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@ -14,6 +15,8 @@
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/engines/puller.h"
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#include "video_core/gpu.h"
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#include "video_core/host1x/host1x.h"
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#include "video_core/host1x/syncpoint_manager.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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@ -60,11 +63,14 @@ void Puller::ProcessBindMethod(const MethodCall& method_call) {
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}
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void Puller::ProcessFenceActionMethod() {
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auto& syncpoint_manager = gpu.Host1x().GetSyncpointManager();
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switch (regs.fence_action.op) {
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case Puller::FenceOperation::Acquire:
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// UNIMPLEMENTED_MSG("Channel Scheduling pending.");
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// WaitFence(regs.fence_action.syncpoint_id, regs.fence_value);
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rasterizer->ReleaseFences();
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while (regs.fence_value >
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syncpoint_manager.GetGuestSyncpointValue(regs.fence_action.syncpoint_id)) {
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rasterizer->ReleaseFences();
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gpu.Scheduler().Yield();
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}
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break;
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case Puller::FenceOperation::Increment:
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rasterizer->SignalSyncPoint(regs.fence_action.syncpoint_id);
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@ -387,6 +387,14 @@ std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
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return impl->AllocateChannel();
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}
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Tegra::Control::Scheduler& GPU::Scheduler() {
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return *impl->scheduler;
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}
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const Tegra::Control::Scheduler& GPU::Scheduler() const {
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return *impl->scheduler;
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}
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void GPU::InitChannel(Control::ChannelState& to_init) {
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impl->InitChannel(to_init);
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}
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@ -124,7 +124,8 @@ class KeplerCompute;
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namespace Control {
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struct ChannelState;
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}
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class Scheduler;
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} // namespace Control
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namespace Host1x {
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class Host1x;
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const;
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/// Returns GPU Channel Scheduler.
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[[nodiscard]] Tegra::Control::Scheduler& Scheduler();
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/// Returns GPU Channel Scheduler.
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[[nodiscard]] const Tegra::Control::Scheduler& Scheduler() const;
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[[nodiscard]] u64 GetTicks() const;
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[[nodiscard]] bool IsAsync() const;
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CommandDataContainer next;
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scheduler.Init();
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while (!stop_token.stop_requested()) {
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state.queue.PopWait(next, stop_token);
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if (stop_token.stop_requested()) {
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break;
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}
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if (auto* submit_list = std::get_if<SubmitListCommand>(&next.data)) {
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scheduler.Push(submit_list->channel, std::move(submit_list->entries));
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if (std::holds_alternative<SubmitListCommand>(next.data)) {
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scheduler.Resume();
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} else if (std::holds_alternative<GPUTickCommand>(next.data)) {
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system.GPU().TickWork();
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} else if (const auto* flush = std::get_if<FlushRegionCommand>(&next.data)) {
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void ThreadManager::StartThread(VideoCore::RendererBase& renderer,
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Core::Frontend::GraphicsContext& context,
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Tegra::Control::Scheduler& scheduler) {
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Tegra::Control::Scheduler& scheduler_) {
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rasterizer = renderer.ReadRasterizer();
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scheduler = &scheduler_;
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thread = std::jthread(RunThread, std::ref(system), std::ref(renderer), std::ref(context),
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std::ref(scheduler), std::ref(state));
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std::ref(scheduler_), std::ref(state));
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}
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void ThreadManager::SubmitList(s32 channel, Tegra::CommandList&& entries) {
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PushCommand(SubmitListCommand(channel, std::move(entries)));
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scheduler->Push(channel, std::move(entries));
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PushCommand(SubmitListCommand());
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}
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void ThreadManager::FlushRegion(DAddr addr, u64 size) {
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namespace VideoCommon::GPUThread {
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/// Command to signal to the GPU thread that a command list is ready for processing
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struct SubmitListCommand final {
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explicit SubmitListCommand(s32 channel_, Tegra::CommandList&& entries_)
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: channel{channel_}, entries{std::move(entries_)} {}
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s32 channel;
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Tegra::CommandList entries;
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};
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struct SubmitListCommand final {};
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/// Command to signal to the GPU thread to flush a region
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struct FlushRegionCommand final {
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private:
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/// Pushes a command to be executed by the GPU thread
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u64 PushCommand(CommandData&& command_data, bool block = false);
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Tegra::Control::Scheduler* scheduler;
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Core::System& system;
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const bool is_async;
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